ISL9N322AP3 Datasheet, PDF (8/11 Pages) Fairchild Semiconductor – N-Channel Logic Level PWM Optimized UltraFET Trench Power MOSFETs

PSPICE Electrical Model
.SUBCKT ISL9N322AP3 2 1 3 ;
CA 12 8 7e-10
CB 15 14 7e-10
CIN 6 8 9.1e-10
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 32.08
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
LDRAIN 2 5 1e-9
LGATE 1 9 4.53e-9
LSOURCE 3 7 5.38e-9
GATE
1
rev April 2001
DPLCAP ₅
10
RSLC2
RSLC1
51
5
51
ESLC
DBREAK
11
LGATE
RLGATE
-
ESG
6
8
+
EVTEMP
RGATE _{+ 18 - 6}
9
20 ²²
EVTHRES
+ ₁₉ -
8
50
RDRAIN
16
21
+
17
EBREAK 18
-
MWEAK
MMED
MSTRO
CIN
8
7
LDRAIN
DRAIN
2
RLDRAIN
DBODY
LSOURCE
SOURCE
3
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 1.2e-3
RGATE 9 20 2.59
RLDRAIN 2 5 10
RLGATE 1 9 45.3
RLSOURCE 3 7 53.8
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 1.3e-2
RVTHRES 22 8 RVTHRESMOD 1
S1A
12 ₁₃
8
S2A
14
15
13
S1B
S2B
CA
13
CB
+
+ ¹⁴
EGS
6
8
-
EDS
5
8
-
RSOURCE
RLSOURCE
RBREAK
17
18
RVTEMP
19
IT
-
VBAT
+
8
22
RVTHRES
RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*110),6))}
.MODEL DBODYMOD D (IS = 8.3e-12 N = 1.08 RS = 9.9e-3 TRS1 = 8.9e-4 TRS2 = 1e-6 XTI = 2.7 CJO = 6.2e-10 TT = 7e-11 M
= 0.62)
.MODEL DBREAKMOD D (RS = 6e-1 TRS1 = 1e-3 TRS2 = -8.5e-6)
.MODEL DPLCAPMOD D (CJO = 3.1e-10 IS = 1e-30 N = 10 M = 0.46)
.MODEL MMEDMOD NMOS (VTO = 1.95 KP = 3.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.59)
.MODEL MSTROMOD NMOS (VTO = 2.32 KP = 35 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.6 KP = 0.05 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 25.9 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1e-3 TC2 = -7e-7)
.MODEL RDRAINMOD RES (TC1 = 3.4e-2 TC2 = 1e-4)
.MODEL RSLCMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -2.2e-3 TC2 = -8e-6)
.MODEL RVTEMPMOD RES (TC1 = -2e-3 TC2 = 1.05e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.0 VOFF = -1.5)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.5 VOFF = -4.0)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.5 VOFF = 0.3)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.3 VOFF = -0.5)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
©2002 Fairchild Semiconductor Corporation
Rev. B, January 2002