FXLP34_11 Datasheet, PDF (8/12 Pages) Fairchild Semiconductor – Single Bit Uni-Directional Translator

Translator Power-up Sequence Recommendations
To ensure that the system does not experience
unnecessary I_CC current draw, bus contention, or
oscillations during power-up; adhere to the following
guidelines. This device is designed with the output pin(s)
supplied by V_CC and the input pin(s) supplied by V_CC1.
The first recommendation is to begin by powering up the
input side of the device with V_CC1. The Input pin(s)
should be ramped with or ahead of V_CC1 or held LOW.
This guards against bus contentions and oscillations as
all inputs and the input V_CC1 are powered at the same
time. The output V_CC can then be powered to the target
voltage level to which the device will translate. The
output pin(s) then translate to logic levels dictated by the
output V_CC levels.
Upon completion of these steps, the device can be
configured for the desired operation. Following these
steps helps prevent possible damage to the translator
device as well as other system components.
AC Loadings and Waveforms
Figure 3. AC Test Circuit
Figure 4. Waveform for Inverting and Non-Inverting Functions
Table 1. AC Load Table
Symbol
V_mi
V_mo
3.3V ±0.3V
1.5V
1.5V
2.5V ±0.2V
V_CC1/2
V_CC/2
V_CC
1.8V ±0.15V 1.5V ±0.10V
V_CC1/2
V_CC/2
V_CC1/2
V_CC/2
1.2V ±0.10V
V_CC1/2
V_CC/2
1.0V
V_CC1/2
V_CC/2
© 2006 Fairchild Semiconductor Corporation
FXLP34 • Rev. 1.0.4
8
www.fairchildsemi.com