FMS6690_06 Datasheet, PDF (8/12 Pages) Fairchild Semiconductor – Six Channel, 6th Order SD/PS/HD Video Filter Driver

The same method can be used for biased signals with the addi-
tion of a pull-up resistor to make sure the clamp never operates.
The internal pull-down resistance is 800kΩ ±20% so the exter-
nal resistance should be 7.5MΩ to set the DC level to 500mV. If
a pull-up resistance less than 7.5MΩ is desired, an external
pull-down can be added such that the DC input level is set to
500mV.
External Video
source must
7.5MΩ
be AC-coupled. ^0.1u
LCVF
75Ω
Bias
Input
75Ω
500mV +/-350mV
Figure 17. Biased SCART with DC-coupled Outputs
The same circuits can be used with AC-coupled outputs if
desired.
DVD or
STB
SoC
DAC
Output
0V - 1.4V
LCVF
Clamp
Inactive
75Ω
220u
Figure 18. DC-coupled Inputs, AC-coupled Outputs
DVD or
STB
SoC
DAC
Output
0V - 1.4V
0.1u
LCVF
Clamp
Active
75Ω ^220μ
Figure 19. AC-coupled Inputs, AC-coupled Outputs
External video
source must
7.5MΩ
be AC-coupled. ^0.1μ
75Ω
500mV +/-350mV
LCVF
Clamp
Active
75Ω ^220μ
Power Dissipation
The FMS6690 output drive configuration must be considered
when calculating overall power dissipation. Care must be taken
not to exceed the maximum die junction temperature. The fol-
lowing example can be used to calculate the FMS6690’s power
dissipation and internal temperature rise.
T_j = T_A + P_d • Θ_JA
where P_d = P_CH1 + P_CH2 + P_CHx
and P_CHx = V_s • I_CH - (V_O2/R_L)
where
V_O = 2V_in + 0.280V
I_CH = (I_CC / 6) + (V_O/R_L)
V_in = RMS value of input signal
I_CC = 60mA
V_s = 5V
R_L = channel load resistance
Board layout can also affect thermal characteristics. Refer to the
Layout Considerations Section for more information.
Layout Considerations
General layout and supply bypassing play major roles in high
frequency performance and thermal characteristics. Fairchild
offers a demonstration board, FMS6690DEMO, to use as a
guide for layout and to aid in device testing and characteriza-
tion. The FMS6690DEMO is a 4-layer board with a full power
and ground plane. Following this layout configuration will pro-
vide the optimum performance and thermal characteristics. For
optimum results, follow the steps below as a basis for high fre-
quency layout:
• Include 10µF and 0.1µF ceramic bypass capacitors
• Place the 10µF capacitor within 0.75 inches of the power pin
• Place the 0.1µF capacitor within 0.1 inches of the power pin
• For multi-layer boards, use a large ground plane to help dissi-
pate heat
• For 2 layer boards, use a ground plane that extends beyond
the device by at least 0.5”
• Minimize all trace lengths to reduce series inductances
Figure 20. Biased SCART with AC-coupled Outputs
NOTE: The video tilt or line time distortion will be dominated by
the AC-coupling capacitor. The value may need to be increased
beyond 220µF in order to obtain satisfactory operation in some
applications.
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8
FMS6690 Rev. 2B