FMS6146_08 Datasheet, PDF (8/10 Pages) Fairchild Semiconductor – Low-Cost Six-Channel 4th-Order Standard Defi nition Video Filter Driver

The same method can be used for biased signals, with the
addition of a pull-up resistor to make sure the clamp never
operates. The internal pull-down resistance is 800kΩ
±20%, so the external resistance should be 7.5MΩ to set
the DC level to 500mV as shown in Figure 12.
External video
source must
7.5MΩ
be AC-coupled ^0.1μ
75Ω
500mV +/-350mV
LCVF
75Ω
Bias
Input
Figure 12. Biased SCART with
DC-Coupled Outputs
The same circuits can be used with AC-coupled outputs if
desired.
DVD or
STB
SoC
DAC
Output
0V - 1.4V
0.1μ
LCVF
Clamp
Active
75Ω ^220μ
Figure 13. DC-Coupled Inputs,
AC-Coupled Outputs
DVD or
STB
SoC
DAC
Output
0V - 1.4V
0.1μ
LCVF
Clamp
Active
75Ω ^220μ
Figure 14. AC-Coupled Inputs and Outputs
External video
source must
be AC-Coupled
0V - 1.4V
0.1μ
75Ω
LCVF
Clamp
Active
75Ω ^220μ
Figure 15. Biased SCART with
AC-Coupled Outputs
NOTE: The video tilt or line time distortion is dominated by
the AC-coupling capacitor. The value may need to be incre-
ased beyond 220μF to obtain satisfactory operation in
some applications.
Power Dissipation
The FMS6146 output drive configuration must be considered
when calculating overall power dissipation. Care must be
taken not to exceed the maximum die junction temperature.
The following example can be used to calculate the
FMS6146’s power dissipation and internal temperature rise.
T_j = T_A + P_d • θ_JA
EQ. 1
where: P_d = P_CH1 + P_CH2 + P_CH3 and
EQ. 2
P_CHx = V_CC • I_CH - (V_O²/R_L)
EQ. 3
where: V_O = 2V_IN + 0.280V
EQ. 4
I_CH = (I_CC/3) + (V_O/R_L)
EQ. 5
V_IN = RMS value of input signal
I_CC = 35mA
V_CC = 5V
R_L = channel load resistance
Board layout can also affect thermal characteristics. Refer
to Layout Considerations for more information.
The FMS6146 is specified to operate with output currents
typically less than 50mA, more than sufficient for a dual
(75Ω) video load. Internal amplifiers are current limited to a
maximum of 100mA and should withstand brief-duration
short-circuit conditions; this capability is not guaranteed.
Layout Considerations
General layout and supply bypassing play major roles in
high-frequency performance and thermal characteristics.
Fairchild offers a demonstration board, FMS6146DEMO,
to guide layout and aid device testing and characterizati-
on. The FMS6146DEMO is a four-layer board with full
power and ground planes. Following this layout configu-
ration provides the optimum performance and thermal
characteristics. For optimum results, follow the guidelines
below as a basis for high-frequency layout:
■ Include 1μF and 0.1μF ceramic bypass capacitors.
■ Place the 1μF capacitor within 0.75 inches of the
power pin.
■ Place the 0.1μF capacitor within 0.1 inches of the
power pin.
■ For multi-layer boards, use a large ground plane to help
dissipate heat.
■ For two-layer boards, use a ground plane that extends
beyond the device by at least 0.5 inches.
■ Minimize all trace lengths to reduce series inductances.
© 2006 Fairchild Semiconductor Corporation
FMS6146 Rev. 1.0.9
8
www.fairchildsemi.com