AN-9730 Datasheet, PDF (8/17 Pages) Fairchild Semiconductor – LED Application Design Guide Using Half-Bridge LLC Resonant Converter for 160W Street Lighting

AN-9730
APPLICATION NOTE
Figure 17. Reference Circuit for Design Example of LLC Resonant Half-Bridge Converter
Design Procedure
In this section, a design procedure is presented using the
schematic in Figure 17 as a reference. An integrated
transformer with center tap, secondary side is used and
input is supplied from Power Factor Correction (PFC) pre-
regulator. A DC-DC converter with 160W/115V output
has been selected as a design example. The design
specifications are as follows:
 Nominal input voltage: 400V_DC (output of PFC
stage)
 Output: 115V/1.4A (160W)
 Hold-up time requirement: 30ms (50Hz line freq.)
 DC link capacitor of PFC output: 240µF
[STEP-1] Define System Specifications
Estimated Efficiency (E_ff): The power conversion
efficiency must be estimated to calculate the maximum
input power with a given maximum output power. If no
reference data is available, use E_ff = 0.88~0.92 for low-
voltage output applications and E_ff = 0.92~0.96 for high-
voltage output applications. With the estimated efficiency,
the maximum input power is given as:
P
in

P_o
E _ff
(11)
Input Voltage Range (V_inmin and V_inmax): The maximum
input voltage would be the nominal PFC output voltage as:
V max
in
 V_O.PFC
(12)
Even though the input voltage is regulated as constant by
PFC pre-regulator, it drops during the hold-up time. The
minimum input voltage considering the hold-up time
requirement is given as:
V min
in

V2
O.PFC

2P_inT_HU
C_DL
(13)
where V_O.PFC is the nominal PFC output voltage, T_HU is
a hold-up time, and C_DL is the DC link bulk capacitor.
(Design Example) Assuming the efficiency is 92%,
P_in

P_o
E _ff
 ¹⁶¹  175W
0.92
V max
in
 V_O.PFC

400V
V min
in

V2
O.PFC

2P_inT_HU
C_DL

400²

2 175  30 10^3
240 10^6
 341V
[STEP-2] Determine Maximum and Minimum
Voltage Gains of the Resonant Network
As discussed in the previous section, it is typical to operate
the LLC resonant converter around the resonant frequency
(f_o) to minimize switching frequency variation. Since the
input of the LLC resonant converter is supplied from PFC
output voltage, the converter should be designed to operate
at f_o for the nominal PFC output voltage.
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.1 • 11/16/12
8
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