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HCPL3700S Datasheet, PDF (7/9 Pages) Fairchild Semiconductor – AC/DC TO LOGIC INTERFACE OPTOCOUPLER
AC/DC TO LOGIC INTERFACE
OPTOCOUPLER
HCPL-3700
Pulse
Generator
tr = 5ns
ZO= 50 $
1 AC
2 DC+
VCC 8
.1uf
7 bypass
3 DC-
VO 6
4 AC GND 5
VIN
Pulse Amplitude = 50 V
Pulse Width = 1 ms
f = 100 Hz
Tr = Tf = 1.0 ms (10 - 90%)
+5V
RL
Output
(VO)
Input
(VIN)
t PHL
Output 90%
(VO)
10%
5V
2.5V
t PLH
0V
VO
90%
10%
1.5 V
VOL
tr
tf
Fig. 9. Switching Test Circuit
VFF
I IN
A
B
RCC*
1 AC
VCC 8
2 DC+
.1uf
7 bypass
3 DC-
VO 6
4 AC GND 5
+
V-CM
Pulse Gen
+5V
RL
Output
(VO)
CL**
VCM
VO
* SEE NOTE 8
** CL IS 30 pF, WHICH INCLUDES PROBE
AND STRAY WIRING CAPACITANCE
VO
VCM H
VCM L
5V
Switching Pos. (A)
IIN = 0 mA
VO (Min)
5V CMH
VO (Max)
Switching Pos. (B)
IIN = 3.11 mA
VOL CM L
Fig. 10. Test Circuit for Common Mode Transient Immunity and Typical Waveforms
200003A