FXLP34_06 Datasheet, PDF (7/12 Pages) Fairchild Semiconductor – Single Bit Uni-Directional Translator

Translator Power Up Sequence Recommendations
To insure that the system does not experience unneces-
sary I_CC current draw, bus contention, or oscillations dur-
ing power up, the following guidelines should be adhered
to. This device is designed with the Output pin(s) is sup-
plied by V_CC and the Input pin(s) supplied by V_CC1.
Therefore the first recommendation is to begin by power-
ing up the input side of the device, V_CC1. The Input pin(s)
should be ramped with or ahead of V_CC1 or held LOW.
This will guard against bus contentions and oscillations
as all Inputs and the Input V_CC1 will be powered at the
same time. The Output V_CC can then be powered to the
voltage level that the device will be used to translate to.
The Output pin(s) will then translate to logic levels dic-
tated by the Output V_CC levels.
Upon completion of these steps the device can then be
configured for the users desired operation. Following
these steps will help to prevent possible damage to the
translator device as well as other system components.
AC Loading and Waveforms
V_CC
VCC1 Input
Input
CL pF
RL Ω
Figure 1. AC Test Circuit
Input
10%
Output
tr = 3 ns
90%
90%
tf = 3 ns
VCC1
Vmi
50%
tW
tPLH
10%
tPHL
GND
VCC
Vmo
Vmo
VOL
Symbol
V_mi
V_mo
Figure 2. Waveform for Inverting and Non-Inverting Functions
V_CC
3.3V ±0.3V 2.5V ±0.2V 1.8V ±0.15V 1.5V ±0.10V 1.2V ±0.10V
1.5V
1.5V
V_CC1 / 2
V_CC / 2
V_CC1 / 2
V_CC / 2
V_CC1 / 2
V_CC / 2
V_CC1 / 2
V_CC / 2
1.0V
V_CC1 / 2
V_CC / 2
FXLP34 Rev. 1.0.3
7
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