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FSA5157_08 Datasheet, PDF (7/12 Pages) Fairchild Semiconductor – 0.4Ω Low-Voltage SPDT Analog Switch
AC Loading and Waveforms
GND
Bn
VIN
RS
VSel
GND
A
CCLL
RL VOUT
GND
tRISE = 2.5ns
VCC
Input – S
GND
10%
VOH
Output – VOUT
VOL
tFALL = 2.5ns
90%
VCC/2
90%
VCC/2
10%
90%
90%
tON
tOFF
Notes:
6. RL, RS, and CL are functions of the application environment (see AC Electrical table for specific values).
7. CL includes test fixture and stray capacitance.
Figure 7. Turn-Off Timing
VCC
VB
Control
Input
B0 VCC
A
B11
S
GND
VOUT
RL
CL*
Control VCC
Input
0V
VOUT
*CL includes fixture and stray capacitance
Figure 8. Break-Before-Make Timing
50%
tR = tF = 2.5 ns (10–90%)
tBBM
0.9 x VOUT
VSel
RT
GND
GND
Off-Isolation = 20 Log (VOUT/VIN)
GND
GND
Network Analyzer
RS
VIN
VS
GND
VOUT
RT
GND
Figure 9. Off Isolation
©2006 Fairchild Semiconductor Corporation
FSA5157 Rev. 1.0.3
7
www.fairchildsemi.com