FMS6419_05 Datasheet, PDF (7/10 Pages) Fairchild Semiconductor – Selectable RGB (YUV) HD/SD Video Filter Driver with Y, C, Composite Outputs

FMS6419
DATA SHEET
Applications
DC Levels
At any given time, the input signal’s DC levels must be
between 0.0V and 1.3V to utilize the optimal headroom and
to avoid clipping on the outputs. The Y channel should
nominally have the Sync Tip at ground and be a 1V signal.
The C channel should ride around the 0.5V level. This will
ensure that the filter will utilize the optimal headroom and
avoid clipping.
DC Coupled Output Applications
The 220µF capacitor coupled with the 150Ω termination
forms a high pass filter that blocks the DC while passing the
video frequencies and avoiding tilt. Lower values such as
10µF would create a problem. By AC coupling, the average
DC level is zero. Thus, the output voltages of all channels
will be centered around zero. Alternately, DC coupling the
output of the FMS6419 is allowable, but not recommended.
There are several tradeoffs: The average DC level on the out-
puts will be 2V. Each output will dissipate an additional
40mW nominally. The application will need to accommodate
a 1V DC offset sync tip. Also, it is recommended to limit one
150Ω load per output.
Driving the Digital Pins with 3.3V
or 5V Logic
Either is allowed as long as the V_ih and V_il are
adhered to.
Pin Configuration
IN_MUX 1
R_INA 2
R_INB 3
G_INA 4
G_INB 5
B_INA 6
B_INB 7
CV_MUX 8
NC 9
NC 10
V_SSA 11
AUX_IN 12
C_IN 13
Y_IN 14
FMS6419MS28
28-pin SSOP
28 F_SEL
27 V_SSRGB
26 V_CCA
25 V_SS
24 R_OUT
23 G_OUT
22 B_OUT
21 Y_OUT
20 V_CCO
19 C_OUT
18 CV_OUT
17 NC
16 V_SSYC
15 NC
Note:
Pin Assignments table follows on page 8.
REV. 5C April 2005
7