FMS6346_08 Datasheet, PDF (7/10 Pages) Fairchild Semiconductor – Six Channel, 6th-Order SD/HD Video Filter Driver

The same method can be used for biased signals with the
addition of a pull-up resistor to make sure the clamp never
operates. The internal pull-down resistance is 800kΩ
±20%, so the external resistance should be 7.5MΩ to set
the DC level to 500mV. If a pull-up resistance less than
7.5MΩ is desired, an external pull-down can be added
such that the DC input level is set to 500mV.
External video
source must
7.5MΩ
be AC coupled ^0.1μF
LCVF
75Ω
Bias
Input
75Ω
500mV +/-350mV
Figure 16. Biased SCART with DC-Coupled Outputs
The same circuits can be used with AC-coupled outputs if
desired, as shown in Figure 17.
DVD or
STB
SoC
DAC
Output
0V - 1.4V
LCVF
Clamp
Inactive
75Ω
220µF
Figure 17 DC-Coupled Inputs, AC-Coupled Outputs
DVD or
STB
SoC
DAC
Output
0V - 1.4V
0.1μF
LCVF
Clamp
Active
75Ω ^220μF
Figure 18. AC-Coupled Inputs, AC-Coupled Outputs
External video
source must
7.5MΩ
be AC coupled. ^0.1μF
75Ω
500mV +/-350mV
LCVF
Clamp
Active
75Ω ^220μF
Power Dissipation
The FMS6346 output drive configuration must be consid-
ered when calculating overall power dissipation. Care
must be taken not to exceed the maximum die junction
temperature. The following example can be used to calcu-
late the FMS6346’s power dissipation and internal tem-
perature rise:
T_J = T_A + P_d • θ_JA
where P_d = P_CH1 + P_CH2 + P_CHx
and P_CHx = V_s • I_CH - (V_O2/R_L)
where
V_O = 2V_in + 0.280V
I_CH = (I_CC / 6) + (V_O/R_L)
V_IN = RMS value of input signal
I_CC = 60mA
V_s = 5V
R_L = channel load resistance
Board layout can affect thermal characteristics. Refer to
the Layout Considerations section for more information.
Layout Considerations
General layout and supply bypassing play major roles in
high-frequency performance and thermal characteristics.
Fairchild offers a demonstration board, FMS6346DEMO,
to guide layout and aid device testing and characteriza-
tion. The FMS6346DEMO is a four-layer board with a full
power and ground plane. Following this layout configura-
tion provides the optimum performance and thermal char-
acteristics. For best results, follow the steps below as a
basis for high-frequency layout:
• Include 10μF and 0.1μF ceramic bypass capacitors
• Place the 10μF capacitor within 0.75 inches of the
power pin
• Place the 0.1μF capacitor within 0.1 inches of the
power pin
• For multi-layer boards, use a large ground plane to
help dissipate heat
• For two-layer boards, use a ground plane that extends
beyond the device by at least 0.5 inches
• Minimize all trace lengths to reduce series inductances
Figure 19. Biased SCART with AC-Coupled Outputs
NOTE: The video tilt or line time distortion is dominated by
the AC-coupling capacitor. The value may need to be in-
creased beyond 220μF to obtain satisfactory operation in
some applications.
© 2006 Fairchild Semiconductor
FMS6346 Rev. 1.0.4
7
www.fairchildsemi.com