FAN4822 Datasheet, PDF (7/10 Pages) Fairchild Semiconductor – ZVS Average Current PFC Controller

PRODUCT SPECIFICATION
Q1 Turn-On
The turn-on event consists of the time it takes for the current
through L2 to ramp to the L1 current plus the resonant event
of L2 and the ZVS capacitor. The total event should occur in
a minimum of 350–450ns, but can be longer at the risk of
increasing the total harmonic distortion. Setting these times
equal should minimize conducted and radiated emissions.
t_Q1(OFF) = t_IL2 + t_RES = 400ns
(1)
Where IL2 is equal to IL1.
The value of L2 is calculated to remain in discontinuous-
mode:
L2 = ^V-----^B---^U----^S-----^×----^V-----^R---^M-----^S---⁽--^M----^I--^N----⁾---^×----^t--^I--^L---²-
2 × P_OUT
(2)
The resonant event occurs in 1/4 of a full sinusoidal cycle.
For example, when a 1/4 cycle occurs in 200ns, the fre-
quency is 1.25MHz.
f_RES
=
-----------------¹------------------
2π _{L2 × CZVS}
=
-₄----_×-----^1t--_R----_E---_S--
(3)
Rearranging and solving for L2:
L2 = --⁴-----^×-----^t-^R----^E----^S---²--
π² × C_ZVS
(4)
The resonant capacitor (CZVS) value is found by setting
equations 2 and 4 equal to each other and solving for CZVS.
C_ZVS = -_π---₂----_×--⁴---_V--^×--_B--^t--_UR---_S-^E----^S_×---²--_V-^×---_R----_M--²--_S---^×-₍-_M---^P--_I-_N-^O---₎-^U--_×--^T---_t--_I-_L---₂-
(5)
Application
Figure 3 displays a typical application circuit for a 500W
ZVS PFC supply. Full design details are covered in applica-
tion note 33, FAN4822 Power Factor Correction With Zero
Voltage Resonant Switching.
A. SYSTEM
CLOCK
(INTERNAL)
B. R_TC_T
C. ZVS GATE (Q2)
D. VDS (Q2)
E. PFC GATE (Q1)
F. VDS (Q1)
G. I_L2
FAN4822
t₁
t₃
t₂
Figure 2. Timing Diagrams
REV. 1.0.1 8/10/01
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