FAN4113 Datasheet, PDF (7/10 Pages) Fairchild Semiconductor – 1.2V, 36MHz, Low Power Rail-to-Rail Amplifier

FAN4113
DATA SHEET
Application Information
General Description
The FAN4113 is single supply, general purpose, voltage-feedback
amplifier. The FAN4113 is fabricated on a complimentary bipolar
process, features a rail-to-rail output, and is unity gain stable.
Power Dissipation
The maximum internal power dissipation allowed is directly
related to the maximum junction temperature. If the maximum
junction temperature exceeds 150°C, some performance
degradation will occur. It the maximum junction temperature
exceeds 175°C for an extended time, device failure may occur.
The typical non-inverting circuit schematic is shown in Figure 1.
+V_s
6.8µF
+
In
0.01µF
+
Out
FAN4113
-
R_f
Overdrive Recovery
Overdrive of an amplifier occurs when the output and/or input
ranges are exceeded. The recovery time varies based on
whether the input or output is overdriven and by how much
the ranges are exceeded. The FAN4113 will typically recover
in less than 50ns from an overdrive condition. Figure 3
shows the FAN4113 in an overdriven condition.
G = 5V
V_s = 2.7V
Output
R_g
Input
Figure 1: Typical Non-inverting Configuration
RR Applications and Beyond
The FAN4113 can be used with input signals that exceed
its common mode input voltage range. Simply attenuate the
input signal and increase the gain of the FAN4113, see
Figure 2. First, select A1 so the FAN4113 common voltage
range is not exceeded. Second, select Rf and Rg to get the
desired overall gain for signal Vin. Finally, pick VDC for the
desired output offset.
R₁
+
V_o
* ^Vin
R₂
–
A₁ =
R₂
R₁ + R₂
R_f
R_g
V_DC
Vo
=
A1Vin

¹⁺
Rf
Rg


−V_DC
Rf
Rg
Figure 2: RR Applications and Beyond
Time (200µs/div)
Figure 3: Overdrive Recovery
Driving Capacitive Loads
The Frequency Response vs. CL plot, illustrates the response
of the FAN4113. A small series resistance (Rs) at the output
of the amplifier, illustrated in Figure 4, will improve stability
and settling performance.
+
-
R_f
R_g
R_s
C_L R_L
Figure 4: Typical Topology for driving
a capacitive load
REV. 1 October 2001
7