SPT9101 Datasheet, PDF (6/8 Pages) Fairchild Semiconductor – 125 MSPS SAMPLE-AND-HOLD AMPLIFIER

The RTN pin may be tied to an external voltage to generate
an offset at the output. V_Out must be kept to less than ±2.7 V
typical output swing. V_Out, with an external reference voltage
at the RTN pin, is represented by the following formula:
V_Out = 4 V_IN - 3 V_Ref
where V_Ref = voltage at RTN pin and | V_Out | ≤ 2.7 V
The following options are generally not recommended due to
the possibility of degraded noise performance of the device:
the RTN pin can also be tied to an external resistor to reduce
the gain but performance may degrade due to increased
noise from the external resistor. Also RTN can be left open for
unity gain mode, however, noise will increase.
In all cases, V_IN must be kept to -0.5 V≤ V_IN ≤ +0.5 V for rated
performance.
SAMPLER FOR 12-BIT ADC APPLICATION
The SPT9101 was specifically designed for applications
where improved bandwidth performance is required. Figure 3
shows as simple block diagram of the SPT9101 as a sampler
ahead of the SPT7922 12-bit, 30 MSPS ADC.
Figure 3 - Sampler for 12-Bit ADC
VIN
SPT9101
SPT7922
12
Clock 1
Clock 2
The graph below entitled Improved Dynamic Performance
Using the SPT9101 shows the performance with and without
the SPT9101. The SPT9101 significantly extends the dy-
namic performance range of the converter.
PERFORMANCE CHARACTERISTICS
Droop Rate vs Temperature
40
0
-40
-80
-120
-20
0
20
40
60
80
Temperature (°C)
SPT9101 Hold Mode Distortion vs. Temperature
-65
Input Frequency = 50 MHz
Clock Frequency = 100 MHz
Hold = 4 ns
Track = 6 ns
Worst Harmonic
-60
-50
-25
0
25
50
Temperature (°C)
75
100
SPT9101 Hold Mode Distortion vs Input Frequency
-75
-70
Worst Harmonic
-65
Clock Frequency = 100 MHz
-60
Track = 6 ns
Hold = 4 ns
-55
1
10
100
Input Frequency (MHz)
Improved Dynamic Performance Using the SPT9101
70
SPT9101 & SPT7922
60
50
SPT7922
(FS = 28 MSPS)
40
5
10
15
20
FIN (MHz)
SPT9101
6
12/30/99