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HCPL2503 Datasheet, PDF (6/12 Pages) Fairchild Semiconductor – HIGH SPEED TRANSISTOR OPTOCOUPLERS
HIGH SPEED
TRANSISTOR OPTOCOUPLERS
SINGLE-CHANNEL: 6N135
DUAL-CHANNEL: HCPL-2530
6N136
HCPL-2531
HCPL-2503
HCPL-4502
ISOLATION CHARACTERISTICS (TA = 0 to 70°C Unless otherwise specified)
Characteristics
Test Conditions
Symbol Min Typ** Max Unit
Input-output
insulation leakage current
Withstand insulation test voltage
Resistance (input to output)
Capacitance (input to output)
DC Current gain
Input-Input
Insulation leakage current
Input-Input Resistance
Input-Input Capacitance
(Relative humidity = 45%)
(TA = 25°C, t = 5 s)
(VI-O = 3000 VDC)
(Note 9)
(RH ≤ 50%, TA = 25°C)
(Note 9) ( t = 1 min.)
(Note 9) (VI-O = 500 VDC)
(Note 9) (f = 1 MHz)
(IO = 3 mA, VO = 5 V)
(RH ≤ 45%, VI-I = 500 VDC) (Note 10)
t = 5 s, (HCPL-2530/2531 only)
(VI-I = 500 VDC) (Note 10)
(HCPL-2530/2531 only)
(f = 1 MHz) (Note 10)
(HCPL-2530/2531 only)
II-O
VISO
RI-O
CI-O
HFE
II-I
RI-I
CI-I
1.0
µA
2500
1012
0.6
150
0.005
1011
0.03
VRMS
Ω
pF
µA
Ω
pF
Notes
1. Derate linearly above 70°C free-air temperature at a rate of 0.8 mA/°C.
2. Derate linearly above 70°C free-air temperature at a rate of 1.6 mA/°C.
3. Derate linearly above 70°C free-air temperature at a rate of 0.9 mW/°C.
4. Derate linearly above 70°C free-air temperature at a rate of 2.0 mW/°C.
5. Current Transfer Ratio is defined as a ratio of output collector current, IO, to the forward LED input current, IF, times 100%.
6. The 4.1 kΩ load represents 1 LSTTL unit load of 0.36 mA and 6.1kΩ pull-up resistor.
7. The 1.9 kΩ load represents 1 TTL unit load of 1.6 mA and 5.6 kΩ pull-up resistor.
8. Common mode transient immunity in logic high level is the maximum tolerable (positive) dVcm/dt on the leading edge of the
common mode pulse signal VCM, to assure that the output will remain in a logic high state (i.e., VO>2.0 V). Common mode
transient immunity in logic low level is the maximum tolerable (negative) dVcm/dt on the trailing edge of the common mode
pulse signal, VCM, to assure that the output will remain in a logic low state (i.e., VO<0.8 V).
9. Device is considered a two terminal device: Pins 1, 2, 3 and 4 are shorted together and Pins 5, 6, 7 and 8 are shorted
together.
10. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together.
I
© 2004 Fairchild Semiconductor Corporation
Page 6 of 12
11/2/04