GTLP6C817 Datasheet, PDF (6/7 Pages) Fairchild Semiconductor – Low Drive GTLP-to-LVTTL 1:6 Clock Driver

Test Circuit and Timing Waveforms
Test Circuit for A Outputs
Test Circuit for B Outputs
Note A: C_L includes probes and jig capacitance.
Voltage Waveform - Propagation Delay Times
Note A: C_L includes probes and jig capacitance.
Note B: For B Port C_L = 30 pF is used for worst case.
Voltage Waveform - Enable and Disable Times
Output Waveform 1 is for an output with internal conditions such that the
output is LOW except when disabled by the control output
Output Waveforms 2 is for an output with internal conditions such that the
output is HIGH except when disabled by the control output
Input and Measure Conditions
A or LVTTL
Pins
B or GTLP
Pins
V_inHIGH
V_CC
1.5
V_inLOW
0.0
0.0
V_M
V_CC/2
1.0
V_X
V_OL + 0.3V
N/A
V_Y
V_OH + 0.3V
N/A
All input pulses have the following characteristics: Frequency = 10MHz, t_RISE = t_FALL = 2 ns, Z_O = 50Ω.
The outputs are measured one at a time with one transition per measurement.
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