 English |
|
|
|
|
|
|
|
| GTLP6C816 Datasheet, PDF (6/7 Pages) Fairchild Semiconductor – GTLP-to-TTL 1:6 Clock Driver | |||
| |||
| ◁ |
Test Circuit and Timing Waveforms
Test Circuit for A Outputs
Test Circuit for B Outputs
Note A: CL includes probes and jig capacitance.
Note B: For B-Port CL = 30 pF is used for worst case.
Note A: CL includes probes and jig capacitance.
Voltage Waveforms Enable and Disable Times A-Port
Voltage Waveforms Propagation Delay (Vm = VCC/2 for A-Port and 1.0 for B-Port)
www.fairchildsemi.com
6
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese