FXLP34 Datasheet, PDF (6/11 Pages) Fairchild Semiconductor – Single Bit Uni-Directional Translator

AC Electrical Characteristics (Continued)
Symbol
Parameter
t_PHL
Propagation Delay
t_PLH
Output Translation
V_CC (V) = 1.2
t_PHL
Propagation Delay
t_PLH
Output Translation
V_CC (V) = 1.5
t_PHL
Propagation Delay
t_PLH
Output Translation
V_CC (V) = 1.8
t_PHL
Propagation Delay
t_PLH
Output Translation
V_CC (V) = 2.5
t_PHL
Propagation Delay
t_PLH
Output Translation
V_CC (V) = 3.3
C_IN
C_OUT
C_PD
Input Capacitance
Output Capacitance
Power Dissipation
Capacitance
V_CC1
(V)
1.0
1.10 to 1.30
1.40 to 1.60
1.65 to 1.95
2.30 to 2.70
3.00 to 3.60
1.0
1.10 to 1.30
1.40 to 1.60
1.65 to 1.95
2.30 to 2.70
3.00 to 3.60
1.0
1.10 to 1.30
1.40 to 1.60
1.65 to 1.95
2.30 to 2.70
3.00 to 3.60
1.0
1.10 to 1.30
1.40 to 1.60
1.65 to 1.95
2.30 to 2.70
3.00 to 3.60
1.0
1.10 to 1.30
1.40 to 1.60
1.65 to 1.95
2.30 to 2.70
3.00 to 3.60
0
0
V_CC/V_CC1 =
(1.0 to 3.60)
T_A = +25°C
Min
Typ
Max
22.0
11.0
19.0
29.0
10.0
18.0
27.5
9.0
17.0
26.7
8.5
16.0
26.1
8.0
16.0
26.0
16.0
6.0
13.0
19.8
5.8
12.0
18.3
5.5
11.0
17.6
5.0
10.0
17.0
4.5
9.0
16.8
15.0
5.0
11.0
16.2
4.5
10.0
14.7
4.0
9.0
13.9
3.5
8.0
13.3
3.5
8.0
13.1
13.0
4.0
8.0
12.7
3.5
7.0
11.2
3.0
6.0
10.5
2.5
5.0
9.9
2.5
5.0
9.7
12.0
3.0
8.0
11.7
2.5
7.0
9.8
2.0
6.0
8.9
1.5
5.0
8.3
1.5
5.0
8.1
2.0
4.0
8.0
T_A = −40°C to +85°C _Units
Min
Max
Conditions
10.0
46.5
9.0
42.6
ns ^{CL = 30 pF}
8.0
36.7
R_L = 1 MΩ
7.0
36.0
6.0
35.9
5.5
25.3
5.0
23.0
ns ^{CL = 30 pF}
4.5
22.4
R_L = 1 MΩ
4.0
21.7
3.5
21.5
5.5
20.4
4.0
19.2
ns ^{CL = 30 pF}
3.5
18.5
R_L = 1 MΩ
3.0
17.9
2.5
17.6
3.5
15.9
3.0
14.3
ns ^{CL = 30 pF}
2.5
13.6
R_L = 1 MΩ
2.0
12.8
2.0
12.5
2.0
15.0
1.5
12.2
ns ^{CL = 30 pF}
1.0
11.5
R_L = 1 MΩ
1.0
10.7
1.0
10.4
pF
pF
V_I = 0V or V_CC1
pF f = 10 MHz
V_CC/V_CC1 = 3.6
Figure
Number
Figures
1, 2
Figures
1, 2
Figures
1, 2
Figures
1, 2
Figures
1, 2
Translator Power Up Sequence Recommendations
To insure that the system does not experience unneces-
sary I_CC current draw, bus contention or oscillations during
power up, the following guidelines should be adhered to.
This device is designed with the Output pin(s) is supplied
by V_CC and the Input pin(s) is supplied by V_CC1. Therefore
the first recommendation is to begin by powering up the
input side of the device, V_CC1. The Input pin(s) should be
ramped with or ahead of V_CC1 or held LOW. This will guard
against bus contentions and oscillations as all Inputs and
the Input V_CC1 will be powered at the same time. The Out-
put V_CC can then be powered to the voltage level that the
device will be used to translate to. The Output pin(s) will
then translate to logic levels dictated by the Output V_CC
levels.
Upon completion of these steps the device can then be
configured for the users desired operation. Following these
steps will help to prevent possible damage to the translator
device as well as other system components.
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