FMS6363_08 Datasheet, PDF (6/9 Pages) Fairchild Semiconductor – Low-Cost, Three-Channel, 6th-Order, High-Definition, Video Filter Driver

The same method can be used for biased signals with
the addition of a pull-up resistor to make sure the clamp
never operates. The internal pull-down resistance is
800kΩ ±20%, so the external resistance should be
7.5MΩ to set the DC level to 500mV. If a pull-up
resistance of less than 7.5MΩ desired, add an external
pull-down such that the DC input level is set to 500mV.
External Video
source must
be AC-coupled. ^0.1µ
7.5MΩ
LCVF
75Ω
Bias
Input
75Ω
500mV +/-350mV
Figure 13. Biased SCART with DC-coupled Outputs
DVD or
STB
SoC
DAC
Output
0V - 1.4V
LCVF
Clamp
Inactive
75Ω
220µ
Figure 14. DC-coupled Inputs, AC-coupled Outputs
External video
source must
be AC-coupled. ^0.1µ
7.5MΩ
75Ω
500mV +/-350mV
LCVF
Clamp
Active
75Ω
220µ
Figure 15. Biased SCART with AC-Coupled Outputs
Note: The video tilt or line time distortion is dominated
by the AC-coupling capacitor. The value may need
to be increased beyond 220µF to obtain
satisfactory operation in some applications.
Power Dissipation
The FMS6363 output drive configuration must be
considered when calculating overall power dissipation.
Care must be taken not to exceed the maximum die
junction temperature. The following example can be
used to calculate the FMS6363’s power dissipation and
internal temperature rise.
The FMS6363 is specified to operate with output
currents typically less than 50mA, more than sufficient
for a single (150Ω) video load. Internal amplifiers are
current limited to a maximum of 100mA and should
withstand brief duration, short-circuit conditions;
however, this capability is not guaranteed.
Layout Considerations
Layout and supply bypassing play major roles in high-
frequency performance and thermal characteristics.
For optimum results, follow the steps below as a basis
for high-frequency layout:
ƒ Include 10µF and 0.1μF ceramic bypass capacitors
ƒ Place the 10μF capacitor within 0.75 inches of the
power pin.
ƒ Place the 0.1μF capacitor within 0.1 inches of the
power pin.
ƒ Connect all external ground pins as tightly as
possible, preferably with a large ground plane under
the package.
ƒ Layout channel connections to reduce mutual trace
inductance.
ƒ Minimize all trace lengths to reduce series
inductances. If routing across a board, place device
such that longer traces are at the inputs rather than
the outputs. If using multiple, low-impedance DC-
coupled outputs, special layout techniques may be
employed to help dissipate heat.
If a multilayer board is used, a large ground plane
directly under the device helps reduce package case
temperature.
For dual-layer boards, an extended plane can be used.
Worst-case additional die power due to DC loading can
be estimated at (V_CC2/4R_load) per output channel. This
assumes a constant DC output voltage of V_CC2. For 5V
V_CC with a dual DC video load, add 25/(4•75) = 83mW,
per channel.
T_J= T_A+ P_d• Θ_JA
(1)
where P_d= P_CH1+ P_CH2+ P_CH3
and P_CHx= V_S • I_CH- (V_O2/R_L)
where
V_O = 2V_IN+ 0.280V
I_CH = (I_CC/ 3) + (V_O/R_L)
V_IN= RMS value of input signal
I_CC = 24mA
V_S= 5V
R_L= channel load resistance
Board layout affects thermal characteristics. Refer to the
Layout Considerations section for more information.
© 2005 Fairchild Semiconductor Corporation
FMS6363 • Rev. 1.0.3
6
www.fairchildsemi.com