FM24C16U Datasheet, PDF (6/14 Pages) Fairchild Semiconductor – 16K-Bit Standard 2-Wire Bus Interface Serial EEPROM

Write Cycle Timing
SCL
SDA
8th BIT
ACK
Note:
WORD n
STOP
CONDITION
tWR
START
CONDITION
The write cycle time (t_WR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle.
Typical System Configuration
VCC
VCC
SDA
SCL
Master
Transmitter/
Receiver
Slave
Receiver
Slave
Transmitter/
Receiver
Master
Transmitter
Master
Transmitter/
Receiver
Note: Due to open drain configuration of SDA and SCL, a bus-level pull-up resistor is called for, (typical value = 4.7kΩ)
6
FM24C16U/17U Rev. A.3
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