FIN1108_10 Datasheet, PDF (6/9 Pages) Fairchild Semiconductor – LVDS 8-Port, High-Speed Repeater

AC Electrical Characteristics
Typical values are at TA=25°C with VCC=3.3V.
Symbol
Parameter
Conditions
Min. Typ. Max. Units
tPLHD
Differential Output
Propagation Delay
LOW-to-HIGH
0.75 1.10 1.75
ns
tPHLD
Differential Output
Propagation Delay
HIGH-to-LOW
0.75 1.10 1.75
ns
tTLHD
tTHLD
tSK(P)
tSK(LH)
tSK(HL)
tSK(PP)
fMAX
tPZHD
Differential Output Rise
Time (20% to 80%)
Differential Output Fall
Time (80% to 20%)
Pulse Skew
|tPLH - tPHL|
RL=100Ω, CL=5pF
VID=200mV to 450mV,
VIC= VID/2 to VCC – (VID/2)
Duty Cycle=50%
Figure 3
Channel-to-Channel
Skew⁽¹⁾
Part-to-Part Skew⁽²⁾
Maximum Frequency⁽³⁾⁽⁴⁾
Differential Output
Enable Time from
Z to HIGH
0.29 0.40 0.58
ns
0.29 0.40 0.58
ns
0.02 0.20
ns
0.02 0.15
ns
0.02 0.15
0.5
ns
400 >630
MHz
3.0
5.0
ns
tPZLD
tPHZD
Differential Output
Enable Time from
Z to LOW
Differential Output
Disable Time from
HIGH to Z
RL=100Ω, CL=5pF
Figure 4, Figure 5
3.1
5.0
ns
2.2
5.0
ns
tPLZD
Differential Output
Disable Time from
LOW to Z
2.5
5.0
ns
tDJ
LVDS Data Jitter,
Deterministic
VID=300mV, PRBS=2²³-1,
VIC=1.2V at 800Mbps
80
135
ps
tRJ
LVDS Clock Jitter,
Random (RMS)
VID=300mV
VIC=1.2V at 400Mbps
1.9
3.5
ps
Notes:
1. tSK(LH), tSK(HL) is the skew between specified outputs of a single device when the outputs have identical loads and
are switching in the same direction.
2. tSK(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two
devices switching in the same direction (either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with
the same supply voltage, same temperature, and have identical test circuits.
3. Passing criteria for maximum frequency is the output VOD >250mV and the duty cycle is better than 45% / 55%
with all channels switching.
4. Output loading is transmission-line environment only; CL is <1pF of stray test fixture capacitance.
© 2002 Fairchild Semiconductor Corporation
FIN1108 • Rev. 1.0.4
6
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