FAN5336_07 Datasheet, PDF (6/10 Pages) Fairchild Semiconductor – 1.5MHz Boost Regulator with 33V Integrated FET Switch

Block Diagram
SHDN
V_IN
SW
3
1
6
FB 4
Shutdown
Circuitry
FB
1.15 x V_REF
+
Comp
-
-
Error
Amp
+
Thermal
Shutdown
+
Comp
-
R
n
R
Q Driver
Ramp
Generator
RS
Current Limit
Comparator _{- +}
Oscillator
+
Amp
0.03
-
Reference
Soft-Start
5
2
NC
GND
Figure 10. Block Diagram
Circuit Description
The FAN5336 is a pulse-width modulated (PWM)
current-mode boost converter. The FAN5336 improves
the performance of battery-powered equipment by
significantly minimizing the spectral distribution of noise
at the input caused by the switching action of the regula-
tor. To facilitate effective noise filtering, the switching
frequency was chosen to be high, 1.5MHz. An internal
soft-start circuit minimizes in-rush currents. The timing of
the soft-start circuit was chosen to reach 95% of the
nominal output voltage within 5ms following an enable
command when V_IN = 2.7V, V_OUT = 21V, I_LOAD = 35mA
and C_{OUT (EFFECTIVE)} = 4.7µF.
The device architecture is a current-mode controller with
an internal sense resistor connected in series with the N-
channel switch. The voltage at the feedback pin tracks
the output voltage at the cathode of the external Schottky
diode (shown in the test circuit in Figure 3). The error
amplifier amplifies the difference between the feedback
voltage and the internal bandgap reference. The ampli-
fied error voltage serves as a reference voltage to the
PWM comparator. The inverting input of the PWM
comparator consists of the sum of two components: the
amplified control signal received from the 30mΩ current
sense resistor and the ramp generator voltage derived
from the oscillator. The oscillator sets the latch and the
latch turns on the FET switch. Under normal operating
conditions, the PWM comparator resets the latch and
turns off the FET, terminating the pulse. Since the com-
parator input contains information about the output volt-
age and the control loop is arranged to form a negative
feedback loop, the value of the peak inductor current is
adjusted to maintain regulation.
Every time the latch is reset, the FET is turned off and
the current flow through the switch is terminated. The
latch can be reset by other events as well, such as over-
current and over-voltage conditions. Over-current condi-
tion is monitored by the current-limit comparator, which
resets the latch and turns off the switch within each clock
cycle. An over-voltage condition at the feedback (FB) pin
is detected by a fast comparator limiting the duty cycle in
a similar manner to over-current monitoring.
© 2004 Fairchild Semiconductor Corporation
FAN5336 Rev. 1.0.1
6
www.fairchildsemi.com