FAN5331 Datasheet, PDF (6/10 Pages) Fairchild Semiconductor – 1.6MHz Boost Converter with 20V Integrated FET Switch

Block Diagram
FB 3
SHDN
V_IN
4
5
Shutdown
Circuitry
FB
1.15 x V_REF
+
Comp
-
-
Error
Amp
+
Thermal
Shutdown
S
+
Comp
-
Ramp
Generator
Oscillator
Current Limit
Comparator
-+
R
RQ
RS
Reference
Soft-Start
SW
1
n
Driver
+
Amp 0.05
-
2
GND
Figure 4. Block Diagram
Circuit Description
The FAN5331 is a pulse-width modulated (PWM) current-mode
boost converter. The FAN5331 improves the performance of bat-
tery powered equipment by significantly minimizing the spectral
distribution of noise at the input caused by the switching action of
the regulator. In order to facilitate effective noise filtering, the
switching frequency was chosen to be high, 1.6MHz. An internal
soft start circuitry minimizes in-rush currents. The timing of the soft
start circuit was chosen to reach 95% of the nominal output voltage
within maximum 5mS following an enable command when V_IN =
2.7V, V_OUT = 15V, I_LOAD = 35mA and C_{OUT (EFFECTIVE)} = 3.2µF.
The device architecture is that of a current mode controller with
an internal sense resistor connected in series with the N-chan-
nel switch. The voltage at the feedback pin tracks the output
voltage at the cathode of the external Schottky diode (shown in
the test circuit). The error amplifier amplifies the difference
between the feedback voltage and the internal bandgap refer-
ence. The amplified error voltage serves as a reference voltage
to the PWM comparator. The inverting input of the PWM com-
parator consists of the sum of two components: the amplified
control signal received from the 50mΩ current sense resistor
and the ramp generator voltage derived from the oscillator. The
oscillator sets the latch, and the latch turns on the FET switch.
Under normal operating conditions, the PWM comparator resets
the latch and turns off the FET, thus terminating the pulse. Since
the comparator input contains information about the output volt-
age and the control loop is arranged to form a negative feed-
back loop, the value of the peak inductor current will be adjusted
to maintain regulation.
Every time the latch is reset, the FET is turned off and the cur-
rent flow through the switch is terminated. The latch can be
reset by other events as well. Over-current condition is moni-
tored by the current limit comparator which resets the latch and
turns off the switch instantaneously within each clock cycle.
Over-voltage condition is detected by a fast comparator limiting
the duty cycle in a similar manner to over-current monitoring
described above.
Applications Information
Setting the Output Voltage
The internal reference is 1.23V (Typical). The output voltage is
divided by a resistor divider, R1 and R2 to the FB pin. The out-
put voltage is given by
V_OUT
=
V_R
E
F


1
+
R-R----^{12-}
According to this equation, and assuming desired output volt-
age of 15V, good choices for the feedback resistors are,
R₁=150kΩ and R₂=13.4kΩ.
Inductor Selection
The inductor parameters directly related to device performances
are saturation current and dc resistance. The FAN5331 oper-
ates with a typical inductor value of 10µH. The lower the dc
resistance, the higher the efficiency. Usually a trade-off between
inductor size, cost and overall efficiency is needed to make the
optimum choice.
The inductor saturation current should be rated around 1A,
which is the threshold of the internal current limit circuit. This
limit is reached only during the start-up and with heavy load
condition; when this event occurs the converter can shift over in
6
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FAN5331 Rev. 1.0.1