TMC2272A Datasheet, PDF (5/20 Pages) Fairchild Semiconductor – Digital Colorspace Converter 36 Bit Color, 50 MHz

TMC2272A
PRODUCT SPECIFICATION
Pin Descriptions (continued)
Pin Name
Inputs
A_11-0
B_11-0
C_11-0
KA_9-0
KB_9-0
KC_9-0
Outputs
X_11-0
Y_11-0
Z_11-0
CPGA/PPGA/
MPGA
KE Pin Number
Pin Number
E11, D13, E12,
E13, F11, F12,
F13, G13, G11,
G12, H13, H12
B10, A11, B11,
C10, A12, B12,
C11, A13, C12,
B13, C13, D12
A5, C6, B6, A6,
A7, B7, A8, B8,
A9, B9, A10, C9
K13, J11, K12,
L13, L12, K11,
M13, M12, L11,
N13
84, 83, 82, 81,
80, 79, 78, 77,
76, 75, 74, 73
97, 96, 95, 94,
93, 92, 91, 90,
89, 87, 86, 85
111, 110, 109,
108, 107, 105,
104, 103, 101,
100, 99, 98
69, 68, 67, 66,
65, 64, 63, 62,
61, 60
M11, L10, N12, 59, 58, 57, 56,
N11, M10, L9, 55, 54, 53, 52,
N10, M9, N9, L8
51, 50
M8, N8, N7, M7, 49, 48, 47, 45,
N6, M6, N5, M5, 44, 43, 41, 40,
N4, L5
39, 38
B4, A3, A2, B3, 115, 116, 117,
A1, C3, B2, B1, 119, 120, 1, 2, 3,
D3, C2, C1, D2 4, 5, 6, 7
D1, E2, E1, F2, 9, 10, 11, 13, 14,
F1, G2, G1, H1, 15, 17, 18, 23,
K1, J2, J1, H2 22, 21, 19
M4, N3, M3, N2, 37, 36, 35, 33,
M2, L3, N1, L2, 32, 31, 30, 29,
K3, M1, L1, K2 28, 27, 26, 25
Pin Function Description
Data Input A. This is one of three 12-bit wide data input ports.
Data Input B. This is one of three 12-bit wide data input ports.
Data Input C. This is one of three 12-bit wide data input ports.
Coefficient Input KAX, KAY, or KAZ. These are the 10-bit
wide coefficient input ports. The value at each of these three
inputs will update one coefficient register as selected by the
coefficient write select (CWSEL_1-0) on the next clock. See Table
1 and the Functional Block Diagram.
Coefficient Input KBX, KBY, OR KBZ. These are the 10-bit
wide coefficient input ports. The value at each of these three
inputs will update one coefficient register as selected by the
coefficient write select (CWSEL_1-0) on the next clock. See Table
1 and the Functional Block Diagram.
Coefficient Input KCX, KCY, OR KCZ. These are the 10-bit
wide coefficient input ports. The value at each of these three
inputs will update one coefficient register as selected by the
coefficient write select (CWSEL_1-0) on the next clock. See Table
1 and the Functional Block Diagram.
Output X. These are the data outputs. Data are available at the
12-bit registered Output Ports X,Y and Z t_DO after every clock
rising edge.
Output Y. These are the data outputs. Data are available at the
12-bit registered Output Ports X,Y and Z t_DO after every clock
rising edge.
Output Z. These are the data outputs. Data are available at the
12-bit registered Output Ports X,Y and Z t_DO after every clock
rising edge.
Table 1. Coefficient Loading
Input
Input
Input
KA_9-0
KB_9-0
KC_9-0
00
Hold
All
Hold
All
Hold
All
CWSEL_1,0
01
10
Load
Load
KAX
KAY
Load
Load
KBX
KBY
Load
Load
KCX
KCY
11
Load
KAZ
Load
KBZ
Load
KCZ
REV. 1.1.3 10/25/00
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