HCPL2503M Datasheet, PDF (5/13 Pages) Fairchild Semiconductor – High Speed Transistor Optocouplers

PRELIMINARY
Electrical Characteristics (Continued) (T_A = 0 to 70°C unless otherwise specified)
Switching Characteristics (V_CC = 5V)
Symbol Parameter
Test Conditions
Device Min. Typ.* Max. Unit
T_PHL
Propagation Delay
Time to Logic LOW
T_A = 25°C, R_L = 4.1kΩ,
I_F = 16mA⁽⁶⁾ (Fig. 7)
R_L = 1.9kΩ, I_F = 16mA,
T_A = 25°C⁽⁷⁾ (Fig. 7)
R_L = 4.1kΩ, I_F = 16mA⁽⁶⁾ (Fig. 7)
R_L = 1.9kΩ, I_F = 16mA⁽⁷⁾ (Fig. 7)
T_PLH
Propagation Delay
Time to Logic HIGH
T_A = 25°C, (R_L = 4.1kΩ,
I_F = 16mA⁽⁶⁾ (Fig. 7)
R_L = 1.9kΩ, I_F = 16mA⁽⁷⁾ (Fig. 7)
T_A = 25°C
R_L = 4.1kΩ, I_F = 16mA⁽⁶⁾ (Fig. 7)
R_L = 1.9kΩ, I_F = 16mA⁽⁷⁾ (Fig. 7)
6N135M
HCPL2530M
6N136M
HCPL4502M
HCPL4503M
HCPL2503M
HCPL2531M
6N135M
HCPL2530M
6N136M
HCPL4502M
HCPL4503M
HCPL2503M
HCPL2531M
6N135M
HCPL2530M
6N136M
HCPL4502M
HCPL4503M
HCPL2503M
HCPL2531M
6N135M
HCPL2530M
6N136M
HCPL4502M
HCPL4503M
HCPL2503M
HCPL2531M
0.45 1.5 µs
0.45 0.8 µs
2.0 µs
1.0 µs
0.5 1.5 µs
0.3 0.8 µs
2.0 µs
1.0 µs
|CM_H|
Common Mode
Transient
Immunity at
Logic High
|CM_L|
Common Mode
Transient
Immunity at
Logic Low
I_F = 0mA, V_CM = 10V_P-P,
R_L = 4.1kΩ, T_A = 25°C⁽⁸⁾ (Fig. 8)
I_F = 0mA, V_CM = 10V_P-P,
R_L = 1.9kΩ, T_A = 25°C⁽⁸⁾ (Fig. 8)
I_F = 0mA, V_CM = 1,500V_P-P,
R_L = 1.9kΩ, T_A = 25°C⁽⁸⁾ (Fig. 8)
I_F = 16mA, V_CM = 10V_P-P,
R_L = 4.1kΩ, T_A = 25°C⁽⁸⁾ (Fig. 8)
I_F = 16mA, V_CM = 10V_P-P,
R_L = 1.9kΩ⁽⁸⁾ (Fig. 8)
6N135M
HCPL2530M
6N136M
HCPL4502M
HCPL2503M
HCPL2531M
10,000
10,000
HCPL4503M 15,000 30,000
6N135M
HCPL2530M
6N136M
HCPL4502M
HCPL2503M
HCPL2531M
10,000
10,000
V/µs
V/µs
V/µs
V/µs
I_F = 0mA, V_CM = 1,500V_P-P,
R_L = 1.9kΩ, T_A = 25°C⁽⁸⁾ (Fig. 8)
HCPL4503M 15,000 30,000
** All Typicals at T_A = 25°C
Notes:
6. The 4.1kΩ load represents 1 LSTTL unit load of 0.36mA and 6.1kΩ pull-up resistor.
7. The 1.9kΩ load represents 1 TTL unit load of 1.6mA and 5.6kΩ pull-up resistor.
8. Common mode transient immunity in logic high level is the maximum tolerable (positive) dV_cm/dt on the leading edge
of the common mode pulse signal V_CM, to assure that the output will remain in a logic high state (i.e., V_O > 2.0V).
Common mode transient immunity in logic low level is the maximum tolerable (negative) dV_cm/dt on the trailing edge
of the common mode pulse signal, V_CM, to assure that the output will remain in a logic low state (i.e., V_O < 0.8V).
©2008 Fairchild Semiconductor Corporation
6N13XM, HCPLXXXM Rev. 1.0.1
5
www.fairchildsemi.com