HCPL0453_09 Datasheet, PDF (5/12 Pages) Fairchild Semiconductor – Single Channel: HCPL0452 HCPL0453 HCPL0500 HCPL0501 Dual Channel: HCPL0530 HCPL0531 HCPL0534

Notes
1 Current Transfer Ratio is designed as a ratio of output collector current, I_O, to the forward LED input current, I_F, times
100%.
2. The 4.1 kΩ load represents 1 LSTTL unit load of 0.36 mA and 6.1kΩ pull-up resistor.
3. The 1.9 kΩ load represents 1 TTL unit load of 1.6 mA and 5.6 kΩ pull-up resistor.
4. Common mode transient immunity in logic high level is the maximum tolerable (positive) dV_cm/dt on the leading edge
of the common mode pulse signal V_CM, to assure that the output will remain in a logic high state (i.e., V_O>2.0 V).
Common mode transient immunity in logic low level is the maximum tolerable (negative) dV_cm/dt on the trailing edge
of the common mode pulse signal, V_CM, to assure that the output will remain in a logic low state (i.e., V_O<0.8 V).
5. Device is considered a two terminal device: Pins 1, 2, 3 and 4 are shorted together and Pins 5, 6, 7 and 8 are
shorted together.
6. 2500 VAC RMS for 1 minute duration is equivalent to 3000 VAC RMS for 1 second duration.
©2003 Fairchild Semiconductor Corporation
HCPL0XXX Rev. 1.0.4
5
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