GTLP1B151 Datasheet, PDF (5/7 Pages) Fairchild Semiconductor – 1-Bit LVTTL/GTLP Transceiver with Separate LVTTL Port and Feedback Path

Test Circuits and Timing Waveforms
Test Circuit for C Outputs
Test Circuit for B Outputs
Test
S
t_PLH/t_PHL OPEN
t_PLZ/t_PZL 6V
t_PHZ/t_PZH GND
Note: C_L includes probes and Jig capacitance.
Voltage Waveforms Propagation Delay
Note: C_L includes probes and Jig capacitance.
Note: For B Port, C_L = 30 pF is used for worst case.
Voltage Waveform Enable and Disable Times
V_INHIGH
V_INLOW
V_M
V_X
V_Y
A or LVTTL
Pins
V_CC
0.0
V_CC/2
V_OL + 0.3V
V_OH − 0.3V
B or GTLP
Pins
1.5
0.0
1.0
N/A
N/A
Note: Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the output control.
Note: All input pulses have the following characteristics:
Frequency = 10MHz, t_RISE = t_FALL = 2 ns (10% to 90%), Z_O = 50Ω. The outputs are measured one at a time with one transition per measurement.
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