FMS6501_07 Datasheet, PDF(5/14 Page) Fairchild Semiconductor – 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers

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FMS6501_07 Datasheet, PDF (5/14 Pages) Fairchild Semiconductor – 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers

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Digital Interface

The I2C-compatible interface is used to program output

enables, input to output routing, input clamp / bias, and

output gain. The I2C address of the FMS6501 is 0x06

(0000 0110) with the ability to offset it to 0x86 (1000

0110) by tying the ADDR pin high.

Both data and address data, of eight bits each, are writ-

ten to the I2C address to access all the control functions.

There are separate internal addresses for each output.

Each outputâs address includes bits to select an input

channel, adjust the output gain, and enable or disable

the output amplifier. More than one output can select the

same input channel for one-to-many routing. When the

outputs are disabled, they are placed in a high-imped-

ance state. This allows multiple FMS6501 devices to be

paralleled to create a larger switch matrix. Typical output

power-up time is less than 500ns.

The clamp / bias control bits are written to their own

internal address, since they should always remain the

same regardless of signal routing. They are set based on

the input signal connected to the FMS6501.

All undefined addresses may be written without effect.

Output Control Register Contents and Defaults

Control Name Width

Enable

1 bit

Type Default Bit(s)

Description

Write

Channel Enable: 1=Enable, 0=Power Down(1)

Gain

Inx

2 bits Write

5 bits Write

6:5 Channel Gain: 00=6dB, 01=7dB, 10=8dB, 11=9dB

4:0 Input selected to drive this output: 00000=OFF(2),

00001=IN1, 00010=IN2... 01100=IN12

Notes:

1. Power down places the output in a high-impedance state so multiple FMS6501 devices may be paralleled. Power

down also de-selects any input routed to the specified output.

2. When all inputs are OFF, the amplifier input is tied to approximately 150mV and the output goes to approximately

300mV with the 6dB gain setting.

Output Control Register MAP

Name Address Bit 7 Bit 6

Bit5 Bit4(1) Bit3

Bit2

OUT1

0x01

Enable Gain1 Gain0

IN4

IN3

IN2

OUT2

0x02

Enable Gain1 Gain0

IN4

IN3

IN2

OUT3

0x03

Enable Gain1 Gain0

IN4

IN3

IN2

OUT4

0x04

Enable Gain1 Gain0

IN4

IN3

IN2

OUT5

0x05

Enable Gain1 Gain0

IN4

IN3

IN2

OUT6

0x06

Enable Gain1 Gain0

IN4

IN3

IN2

OUT7

0x07

Enable Gain1 Gain0

IN4

IN3

IN2

OUT8

0x08

Enable Gain1 Gain0

IN4

IN3

IN2

OUT9

0x09

Enable Gain1 Gain0

IN4

IN3

IN2

Notes:

1. IN4 is provided for forward compatibility and should always be written as â0â in the FMS6501.

Bit1

IN1

Bit0

IN0

Clamp Control Register Contents and Defaults

Control Name Width Type Default

Clmp

1 bit

Write

Bit(s)

7:0

Description

Clamp / Bias selection: 1 = Clamp, 0 = Bias

Clamp Control Register Map

CLAMP1

0x1D

Clmp8

CLAMP2

0x1E

Resvâd

Bit 6

Clmp7

Resvâd

Bit5

Clmp6

Resvâd

Bit4

Clmp5

Resvâd

Bit3

Clmp4

Clmp12

Bit2

Clmp3

Clmp11

Bit1

Clmp2

Clmp10

Bit0

Clmp1

Clmp9

FMS6501 Rev. 1.0.4

www.fairchildsemi.com

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