FMS6408 Datasheet, PDF (5/9 Pages) Fairchild Semiconductor – Triple Video Filter Driver for RGB and YUV Signals

FMS6408
Pin Configuration
DATA SHEET
Y_{INA 1}
U_{INA 2}
V_{INA 3}
GND 4
Y_{INB 5}
U_{INB 6}
V_{INB 7}
FMS6408
14-pin
TSSOP
14 VCC
13 ^YOUT
12 BYPASS
11 ^UOUT
10 GND
9 ^VOUT
8 ^INMUX ^(A/B)
Pin#
1
Pin
Y_INA
Type
Input
2
U_INA
Input
3
V_INA
Input
4
GND
Input
5
Y_INB
Input
6
U_INB
Input
7
V_INB
Input
8 IN_MUX (A/B) Input
9
V_OUT
Output
10
GND
Input
11
U_OUT
Output
12 BYPASS Input
(Bypass/Filter)
13
Y_OUT
Output
14
V_CC
Input
Description
Y (Luminance) or Green input A, must be
connected to a signal which includes sync
U or Blue input A
V or Red input A
Must be tied to ground, do not float
Y (Luminance) or Green input B, must be
connected to a signal which includes sync
U or Blue input B
V or Red input B
Mux select, A = ‘1’, B = ‘0’, must be
externally tied high or low
V or Red output
Must to be tied to ground, do not float
U or Blue output
Filter bypass, BYPASS = ‘1’, FILTER = ‘0’,
must be externally tied high or low
Y or Green output
+5V supply
Functional Description
Introduction
This product is a three channel monolithic continuous time
video filter designed for reconstructing YUV, YC CV or
RGB signals from a video D/A source. Inputs should be AC
coupled while outputs can be either AC or DC coupled.
The reconstruction filters approximate a 5th order Butter-
worth response optimized for minimum overshoot and flat
group delay. This provides a maximally flat response in
terms of delay and amplitude. Each of the three outputs is
capable of driving 2Vpp into 75Ω loads.
All channels are clamped during the sync interval to set the
appropriate dc output level. Sync tip clamping greatly reduces
the effective input time constant allowing the use of small
low cost input coupling capacitors. The input will settle to
10mV in 2ms for typical DC shifts present in the video signal.
In most applications the input coupling capacitors are 0.1µF.
The inputs typically sink 1uA of current during active video.
For YUV signals, this translates into a 2mV tilt in a horizon-
tal line at the Y output. During sync, the clamp restores this
leakage current by sourcing an average of 20µA over the
clamp interval. Any change in the coupling capacitor values
will affect the amount of tilt per line. Any reduction in tilt
will come with an increase in settling time.
Sync processing is based on the Y/G input channel in all
operating modes.
Inputs
The inputs will typically be driven by either a low impedance
source of 1Vpp or the output of a 75Ω terminated line driven
by the output of a current DAC. In either case, the inputs
must be capacitively coupled to allow the sync-detect and
DC restore circuitry to operate properly.
Outputs
The outputs are low impedance voltage drivers which can
handle either a single or dual load. A single load consists of
a 75Ω series termination resistor feeding a 75Ω terminated
line for a total load at the part of 150Ω. Even when two loads
are present (75Ω) the driver will produce a full 2Vpp signal
at its output pin. The driver can also be used to drive an AC
coupled single or dual load. When driving a dual load either
output will still function if the other output connection is
inadvertently shorted providing these loads are AC coupled.
REV. 2C August 31, 2004
5