FM24C32U Datasheet, PDF (5/13 Pages) Fairchild Semiconductor – 32K-Bit Standard 2-Wire Bus Interface Serial EEPROM

AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
V_CC x 0.1 to V_CC x 0.9
10 ns
Input & Output Timing Levels V_CC x 0.3 to V_CC x 0.7
Output Load
1 TTL Gate and C_L = 100 pF
AC Testing Input/Output Waveforms
0.9VCC
0.1VCC
0.7VCC
0.3VCC
Read and Write Cycle Limits (Standard and Low V_CC Range 2.7V - 5.5V)
Symbol
Parameter
100 KHz
Min
Max
400 KHz
Min
Max
f_SCL
SCL Clock Frequency
100
400
T_I
Noise Suppression Time Constant at
SCL, SDA Inputs (Minimum V_IN
100
50
Pulse width)
t_AA
SCL Low to SDA Data Out Valid
0.3
3.5
0.1
0.9
t_BUF
Time the Bus Must Be Free before
4.7
1.3
a New Transmission Can Start
t_HD:STA
Start Condition Hold Time
4.0
0.6
t_LOW
Clock Low Period
4.7
1.5
t_HIGH
Clock High Period
4.0
0.6
t_SU:STA
Start Condition Setup Time
4.7
0.6
(for a Repeated Start Condition)
t_HD:DAT
t_SU:DAT
t_R
t_F
t_SU:STO
t_DH
t_WR
(Note 4)
Data in Hold Time
Data in Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
Write Cycle Time
4.5V to 5.5V V_CC
2.7V to 4.5V V_CC
0
0
250
100
1
0.3
300
300
4.7
0.6
300
50
10
10
15
15
Units
KHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
µs
ns
ms
Note 4: The write cycle time (t_WR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the
FM24C32U bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address. Refer
"Write Cycle Timing" diagram.
Bus Timing
SCL
SDA
IN
tSU:STA
SDA
OUT
tF
tLOW
tHD:STA
tHIGH
tR
tLOW
tHD:DAT
tSU:DAT
tAA
tDH
tSU:STO
tBUF
FM24C32U Rev. A.1
5
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