AN-9717 Datasheet, PDF (5/30 Pages) Fairchild Semiconductor – Dual BCM PFC Controller

3. Specifications
www.fairchildsemi.com
This board has been designed and optimized for the following conditions:
Input Voltage Range
Rated Output Power
Output Voltage
(Rated Current)
VIN Nominal : 85~264VAC
VDD Supply : 13VDC~18VDC
400W
Note:
1. Minimum output voltage during the 20ms hold-up time is 330VDC.
400V-1A
ƒ V_LINE = 85~264V_AC
ƒ V_OUT = 400V
ƒ f_SW > 50kHz
ƒ Efficiency > 96% down to 20% load (115V_AC)
ƒ Efficiency > 97% down to 20% load (230V_AC)
ƒ PF > 0.99 at full load
The trip points for the built-in protections are set as below in the evaluation board.
ƒ The non-latching output OVP trip point is set at 108% of the nominal output voltage.
ƒ The latching output OVP trip point is set at 117% of the nominal output voltage.
ƒ The line UVLO (brownout protection) trip point is set at 68V_AC (10V_AC hysteresis).
ƒ The pulse-by-pulse current limit for each MOSFET is set at 9.1A.
The maximum power limit is set at ~120% of the rated output power. The phase
management function permits phase shedding/adding ~15% of the nominal output power
for high line (230V_AC). This level can be programmed by modifying MOT resistor (R6).
© 2010 Fairchild Semiconductor Corporation
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FEB279_FAN9611/12 • Rev. 0.0.2