AN-4150 Datasheet, PDF (5/16 Pages) Fairchild Semiconductor – Design Guidelines for Flyback Converters

AN-4150
APPLICATION NOTE
DC link voltage
Minimum DC link voltage
t₁
D_ch = t₁ / t₂
= 0.2
t₂
[STEP-4] Determine the Transformer Primary-Side
Inductance (L_m)
The conventional quasi-resonant converter employs a
variable frequency control, which makes the optimum
design of the magnetic components difficult. However, FSQ-
series can operate in both CCM and DCM with near constant
switching frequency thanks to the advanced control
technique, which allows engineers to use the conventional
transformer design procedure of PWM converters.
Figure 7. DC Link Voltage Waveform
[STEP-3] Determine the Reflected Output Voltage (V_RO)
Figure 8 shows typical waveforms of the drain voltage of
quasi-resonant flyback converter. When the MOSFET is
turned off, the DC link voltage (V_DC), together with the
output voltage reflected to the primary (V_RO), is imposed on
the MOSFET. The maximum nominal voltage across the
MOSFET (V_dsnom) is:
V_d
n
s
om
=
V_DCmax + V_RO
(EQ 5)
where V_DCmax is as specified in Equation 4. As shown in
Figure 8, the capacitive switching loss of the MOSFET can
be reduced by increasing V_RO. However, this increases the
voltage stress on the MOSFET. Therefore, V_RO should be
determined by a trade-off between the voltage margin of the
MOSFET and the efficiency. It is typical to set V_RO as
60~90V so that V_dsnorm is 430~460V (65~70% of MOSFET
rated voltage).
In respect of EMI, DCM operation is preferred since the
MOSFET is turned on at the minimum drain voltage and the
secondary-side diode is softly turned off when operating in
DCM. The transformer size can be reduced when using
DCM because the average energy storage is low compared to
CCM. However, DCM inherently causes higher RMS
current, which increases the conduction loss of the MOSFET
and the current stress on the output capacitors. When
considering efficiency as well as magnetic components size,
it is typical to design the converter to operate in CCM for
low input voltage condition and in DCM for high input
voltage condition.
The transformer primary side inductance is determined for
the minimum input voltage and full-load condition. Once the
reflected output voltage (V_RO) is determined in STEP-3, the
flyback converter can be simplified, as shown in Figure 9, by
neglecting the voltage drops in MOSFET and diode. The
design rules are a bit different for CCM and DCM.
CCM Design: When designing a converter to operate in
CCM at full load and minimum input voltage condition, the
maximum duty ratio is given by:
-
+
+
V_DC
L_m
V_RO
V_O
-
FPS
-
Drain ⁺
+
C_oss
V_ds
GND
-
D_max
=
--------------V----^R----^O---------------
V_RO + V_DCmin
(EQ 6)
where V_DCmin and V_RO are specified in Equation 3 and
STEP-3, respectively.
With D_max, the primary-side inductance (L_m) of the
transformer is obtained as:
L_m
=
(_{---V----D----C----}^m_----ⁱ_-ⁿ_----⋅_{---D-----m----a---x---})_--²_-
2P_inf_sK_RF
(EQ 7)
V_dsnom
V_DC ^max
V_RO
V_RO
V_dsnom
where V_DCmin is specified in Equation 3, P_in is specified in
STEP-1, f_s is the free-running switching frequency of the
FPS device, and K_RF is the ripple factor, shown in Figure
9. The ripple factor is closely related to the transformer
size and the RMS value of the MOSFET current. It is
typical to set K_RF = 0.5-0.7 for the universal input range.
V_RO
DCM Design: When designing the converter to operate
V_RO
in DCM at full load and minimum input voltage condition,
the maximum duty ratio should be chosen as smaller than
the value obtained in Equation 6, as shown in Figure 9:
0V
Figure 8. Typical Waveform of MOSFET Drain Voltage for
Quasi-Resonant Converter
D_max
<
--------------V----^R----^O---------------
V_RO + V_DCmin
(EQ 8)
Since reducing D_max increases the conduction loss in
© 2006 Fairchild Semiconductor Corporation
FSQ-Series Rev. 1.0.0 10/23/06
5
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