AN-400A Datasheet, PDF (5/8 Pages) Fairchild Semiconductor – Low-Power Green-Mode PWM Flyback Power Controller

AN-400A
flyback power supplies operating in CCM without adding
external components.
The positive ramp added is:
V_SLOPE = V_SL • D
(3)
where V_SL = 0.33V and D = duty cycle.
Actual Power
Limit Point
High Line
Sense Voltage
APPLICATION NOTE
Low Line
Sense Voltage
0
tD
tON1
tON2
Figure 12.Constant Power Limit Compensation
Figure 11.Synchronized Slope Compensation
Over-Temperature Protection (OTP)
A built-in temperature sensing circuit shuts down PWM
output once the junction temperature exceeds 140°C. While
PWM output is shuts down, the V_DD voltage gradually drops
to the UVLO voltage (around 8V). Then V_DD is charged up
to the startup threshold voltage of 17V through the start up
resistor until PWM output is restarted. This “hiccup” mode
protection occurs repeatedly as long as the temperature
remains above 110°C. The temperature hysteresis window
for the OTP circuit is 30°C.
Leading-Edge Blanking (LEB)
A voltage signal proportional to the MOSFET current
develops on the current-sense resistor R_S. Each time the
MOSFET turns on, a spike induced by the diode reverse
recovery and by the output capacitances of the MOSFET
and diode, appears on the sensed signal. A leading-edge
blanking time about 310ns is introduced to avoid premature
termination of MOSFET by the spike. Therefore, only a
small-value RC filter (e.g. 100Ω + 47pF) is required
between the SENSE pin and R_S. A non-inductive resistor for
the R_S is recommended.
Constant Output Power Limit
The maximum output power of a flyback converter can be
generally designed by the current-sense resistor R_S. When
the load increases, the peak inductor current increases
accordingly. When the output current arrives at the
protection value, the OCP comparator dominates the current
control loop. OCP occurs when the current-sense voltage
reaches the threshold value. The output GATE driver is
turned off after a small propagation delay, t_D. The delay
time results in unequal power-limit level under universal
input. In FAN400A, a sawtooth power-limiter is designed to
solve the unequal power-limit problem. As shown in Figure
12, the power limiter is designed as a positive ramp signal
fed to the non-inverting input of OCP comparator. This
results in a lower current limit at high-line input than at low-
line. However, with fixed propagation delay t_D, the peak
primary current would be the same for various line input
voltage. Therefore, the maximum output power can almost
be limited to a constant value within a wide input voltage
range without adding external circuits.
Figure 13.Turn-on Spike
Gate Drive
FAN400A’s output stage is a fast totem-pole driver that can
directly drive MOSFET gate. It is equipped with a voltage
clamping Zener diode to protect MOSFET from damage
caused by undesirable over-drive voltage. The output
voltage is clamped at 17V. An internal pull-down resistor is
used to avoid floating state of gate before startup. A gate
drive resistor in the range of 47 to 100Ω is recommended to
limit the peak gate drive current and provide damping to
prevent oscillations at the MOSFET gate terminal.
© 2008 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 5/29/08
5
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