74LCXH162374 Datasheet, PDF (5/11 Pages) Fairchild Semiconductor – Low Voltage 16-Bit D-Type Flip-Flop with Bushold and 26Ω Series Resistors in Outputs

DC Electrical Characteristics (Continued)
Symbol
Parameter
Conditions
I_I(HOLD)
Bushold Input Minimum
Drive Hold Current
I_I(OD)
Bushold Input Over-Drive
Current to Change State
V_IN = 0.7V
V_IN = 1.7V
V_IN = 0.8V
V_IN = 2.0V
(Note 7)
(Note 8)
(Note 7)
(Note 8)
I_OZ
3-STATE Output Leakage
I_OFF
Power-Off Leakage Current
I_CC
Quiescent Supply Current
∆I_CC
Increase in I_CC per Input
Note 6: Outputs disabled or 3-STATE only.
V_O = V_CC or GND
V_I = V_IH or V_IL
V_O = V_CC
V_I = V_CC or GND
3.6V ≤ V_O ≤ 5.5V (Note 6)
V_IH = V_CC −0.6V
Note 7: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 8: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
V_CC
(V)
2.3
3.0
2.7
3.6
2.3 − 3.6
0
2.3 − 3.6
2.3 − 3.6
2.3 − 3.6
T_A = −40°C to +85°C
Min
Max
45
−45
75
−75
300
−300
450
−450
±5.0
10
20
±20
500
Units
µA
µA
µA
µA
µA
µA
AC Electrical Characteristics
T_A = −40° to +85°C, R_L = 500Ω
Symbol
Parameter
V_CC = 3.3V ± 0.3V
C_L = 50 pF
V_CC = 2.7V
C_L = 50 pF
V_CC = 2.5V ± 0.2V
C_L = 30 pF
Units
Min
Max
Min
Max
Min
Max
f_MAX
Maximum Clock Frequency
170
MHz
t_PHL
Propagation Delay
t_PLH
CP to O_n
1.5
7.0
1.5
7.3
1.5
8.4
ns
1.5
7.0
1.5
7.3
1.5
8.4
t_PZL
Output Enable time
t_PZH
1.5
6.9
1.5
7.1
1.5
9.0
ns
1.5
6.9
1.5
7.1
1.5
9.0
t_PLZ
Output Disable Time
t_PHZ
1.5
6.0
1.5
6.2
1.5
7.2
ns
1.5
6.0
1.5
6.2
1.5
7.2
t_S
Setup Time
2.5
2.5
3.0
ns
t_H
Hold Time
1.5
1.5
2.0
ns
t_W
Pulse Width
3.0
3.0
3.5
ns
t_OSHL
Output to Output Skew (Note 9)
1.0
ns
t_OSLH
1.0
Note 9: Skew is defined as the absolute value of the differences between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t_OSHL) or LOW-to-HIGH (t_OSLH). Parameter guaranteed by design.
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