TMC2192 Datasheet, PDF (47/69 Pages) Fairchild Semiconductor – 10 Bit Encoder

PRODUCT SPECIFICATION
TMC2192
Control Register Definitions (continued)
Vertical Blanking Interval Enable Register (0x19)
7
6
5
4
3
2
1
0
SHORT
T512
HALFEN
VBIENF2
Reg Bit
19 7
19 6
Name
SHORT
T512
19 5
HALFEN
19 4-0 VBIENF2
Description
Test Register. Program LOW.
EH/SL Offset Control Bit.
When LOW, the true value of EH and SL is offset by 256.
When HIGH, the true value of EH and SL is offset by 512.
Half Line Enable.
When LOW, half-line blanking occurs on line 283 (NTSC) or line 23 (PAL).
When HIGH, line 283 (NTSC) or line 23 (PAL) is treated as a full line of
active video.
VBI Active Video Enable, Field 2.
The value of VBIENF2 determines which line blanking stops and active line
for ODD fields in NTSC starting from line 4 to line 35 or an EVEN fields for
PAL starting from line 1 to line 32.
Pedestal Height Register (0x1A)
7
6
5
4
3
2
1
0
Reserved
PEDHGT1
Reg Bit
1A 7
1A 6-0
Name
Reserved
PEDHGT1
Description
Composite Pedestal Height.
PEDHGT1 is a 2’s comp value producing a pedestal height from -22.1 IRE
to 21.7 IRE with .345 IRE steps on the composite data path. The default 7.5
IRE pedestal for NTSC-M results from a hex code of 0010110b.
Closed Caption Register (0x1C)
7
6
5
4
3
2
1
0
CCD1
Reg Bit
1C 7-0
Name
CCD1
Description
First Byte of CC Data.
Bit 0 is the LSB. The MSB will be overwritten by an ODD Parity Bit if
CCPAR is HIGH.
REV. 1.0.0 8/13/03
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