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FOD070L Datasheet, PDF (4/17 Pages) Fairchild Semiconductor – LVTTL/LVCMOS COMPATIBLE LOW INPUT CURRENT HIGH GAIN SPLIT DARLINGTON OPTOCOUPLERS
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SINGLE CHANNEL:
DUAL CHANNEL:
LVTTL/LVCMOS COMPATIBLE LOW INPUT
CURRENT HIGH GAIN SPLIT DARLINGTON
OPTOCOUPLERS
FOD070L
FOD073L
FOD270L
ISOLATION CHARACTERISTICS (TA = 0 to 70°C Unless otherwise specified)
Characteristics
Test Conditions Symbol Device Min Typ** Max Unit
Input-output
insulation leakage current
(Relative humidity = 45%)
(TA = 25°C, t = 5 s)
(VI-O = 3000 VDC)
II-O
(Note 4)
Withstand insulation
test voltage
(RH ≤ 50%, TA = 25°C)
(Note 4) ( t = 1 min.)
VISO
Resistance (input to output)
(Note 4) (VI-O = 500 VDC) RI-O
Capacitance (input to output)
(Note 4,5) (f = 1 MHz) CI-O
Input-Input
Insulation leakage current
(RH ≤ 45%, VI-I = 500 VDC (Note 6) II-I
Input-Input Resistance
Input-Input Capacitance
(VI-I = 500 VDC) (Note 6) RI-I
(f = 1 MHz) (Note 6) CI-I
ALL
FOD070L
FOD073L
FOD270L
ALL
ALL
2500
5000
FOD073L 0.005
FOD073L
FOD073L
1012
0.7
1011
0.03
1.0
µA
VRMS
Ω
pF
µA
Ω
pF
** All typicals at TA = 25°C
NOTES
1. Current Transfer Ratio is defined as a ratio of output collector current, IO, to the forward LED input current, IF, times 100%.
2. Pin 7 open. (FOD070L and FOD270L only)
3. Common mode transient immunity in logic high level is the maximum tolerable (positive) dVCM/dt on the leading edge of the
common mode pulse signal, VCM, to assure that the output will remain in a logic high state (i.e., VO>2.0 V). Common mode
transient immunity in logic low level is the maximum tolerable (negative) dVCM/dt on the trailing edge of the common mode
pulse signal, VCM, to assure that the output will remain in a logic low state (i.e., VO<0.8 V).
4. Device is considered a two terminal device: Pins 1, 2, 3 and 4 are shorted together and Pins 5, 6, 7 and 8 are shorted together.
5. For dual channel devices, CI-O is measured by shorting pins 1 and 2 or pins 3 and 4 together and pins 5 through 8 shorted
together.
6. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together.
© 2004 Fairchild Semiconductor Corporation
Page 4 of 17
8/10/04
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