FDMF6704V Datasheet, PDF (4/13 Pages) Fairchild Semiconductor – The Xtra Small, High Performance, High Frequency DrMOS Module with LDO

Electrical Characteristics
V_IN = 12 V, V_DRV = 12 V, T_A = 25 °C unless otherwise noted.
Parameter
Symbol
Conditions
Operating Quiescent Current
IQ
Internal 5V Regulator
PWM = GND
PWM = V_CIN
Input Voltage
Input Current
Output voltage
Power Dissipation
VCIN Capacitor
Line Regulation
Load Regulation
Short Circuit Current Limit
V_DRV
I_VDRV
V_CIN
P_VDRV
C_VCIN
8V < V_IN < 14V, 1MHz
V_DRV = 8V, I_Load = 5mA
V_DRV = 12V, 1MHz
X7R Ceramic
8V < V_DRV < 14V, I_Load = 5mA
V_DRV = 8V, 5mA < I_Load < 100mA
UVLO Threshold
UVLO COMP Hysteresis
PWM Input
Sink Impedance
PWM to GND
Source Impedance
Tri-State Rising Threshold
PWM to V_CIN
Tri-State Rising Hysteresis
Tri-State Falling Threshold
Tri-State Falling Hysteresis
Tri-State Pin Open
Tri-State Shut Off Time
SMOD# and DISB# Input
High Level Input Voltage
Low Level Input Voltage
Input Bias Current
Propagation Delay Time
PWM = GND, delay between SMOD#
or DISB# from HI to LO to GL from HI
to LO.
High Side Driver
Rise Time
10 % to 90 %
Fall Time
90 % to 10 %
Deadband Time
t_DTHH
GL going LO to GH going HI, 10 % to
10 %
Propagation Delay
Low Side Driver
t_PDHL
PMW going LO to GH going LO
Rise Time
10 % to 90 %
Fall Time
90 % to 10 %
Deadband Time
t_DTLH
VSWH going LO to GL going HI, 10
% to 10 %
Propagation Delay
250 ns Time Out Circuit
t_PDLL
PWM going HI to GL going LO
250 ns Time Delay
Delay between GH from HI to LO and
GL from LO to HI if VSWH is high.
Min
8
4.8
4.7
3.2
1.2
2
-2
Typ Max Units
2
mA
2
14
V
36
mA
5
5.2
V
250
mW
10
F
20
mV
75
mV
200
mA
7.5
V
0.5
V
10
k
10
k
3.4
3.6
V
100
mV
1.4
1.6
V
100
mV
2.5
V
100
ns
V
0.8
V
2
A
15
ns
25
ns
20
ns
25
ns
10
ns
25
ns
20
ns
20
ns
10
ns
250
ns
4
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FDMF6704V Rev. C