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| CD4724BC_02 Datasheet, PDF (4/7 Pages) Fairchild Semiconductor – 8-Bit Addressable Latch | |||
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AC Electrical Characteristics (Note 4)
TA = 25°C, CL = 50 pF, RL = 200k, Input tr = tf = 20 ns, unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tPHL, tPLH
tPLH, tPHL
tPHL
tPLH, tPHL
tTHL, tTLH
TWH, TWL
tWH, tWL
tWH
tSU
tH
tSU
tH
CPD
Propagation Delay
Data to Output
Propagation Delay
Enable to Output
Propagation Delay
Clear to Output
Propagation Delay
Address to Output
Transition Time
(Any Output)
Minimum Data
Pulse Width
Minimum Address
Pulse Width
Minimum Clear
Pulse Width
Minimum Setup Time
Data to E
Minimum Hold Time
Data to E
Minimum Setup Time
Address to E
Minimum Hold Time
Address to E
Power Dissipation
Capacitance
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
Per Package
(Note 5)
200
400
75
150
ns
50
100
200
400
80
160
ns
60
120
175
350
80
160
ns
65
130
225
450
100
200
ns
75
150
100
200
50
100
ns
40
80
100
200
50
100
ns
40
80
200
400
100
200
ns
65
125
75
150
40
75
ns
25
50
40
80
20
40
ns
15
30
60
120
30
60
ns
25
50
â15
50
0
30
ns
0
20
â50
15
â20
10
ns
â15
5
100
pF
CIN
Input Capacitance
Any Input
Note 4: AC Parameters are guaranteed by DC correlated testing.
5.0
7.5
pF
Note 5: Dynamic power dissipation (PD) is given by: PD = (CPD + CL) VCC2f + PQ; where CL = load capacitance; f = frequency of operation; for further details,
see Application Note AN-90, âFamily Characteristicsâ.
www.fairchildsemi.com
4
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