CD4724BC Datasheet, PDF (4/7 Pages) Fairchild Semiconductor – 8-Bit Addressable Latch

AC Electrical Characteristics (Note 4)
T_A = 25°C, C_L = 50 pF, R_L = 200k, Input t_r = t_f = 20 ns, unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t_{PHL, tPLH}
t_PLH, t_PHL
t_PHL
t_PLH, t_PHL
t_THL, t_TLH
T_WH, T_WL
t_WH, t_WL
t_WH
t_SU
t_H
t_SU
t_H
C_PD
Propagation Delay
Data to Output
Propagation Delay
Enable to Output
Propagation Delay
Clear to Output
Propagation Delay
Address to Output
Transition Time
(Any Output)
Minimum Data
Pulse Width
Minimum Address
Pulse Width
Minimum Clear
Pulse Width
Minimum Setup Time
Data to E
Minimum Hold Time
Data to E
Minimum Setup Time
Address to E
Minimum Hold Time
Address to E
Power Dissipation
Capacitance
V_DD = 5V
V_DD = 10V
V_DD = 15V
V_DD = 5V
V_DD = 10V
V_DD = 15V
V_DD = 5V
V_DD = 10V
V_DD = 15V
V_DD = 5V
V_DD = 10V
V_DD = 15V
V_DD = 5V
V_DD = 10V
V_DD = 15V
V_DD = 5V
V_DD = 10V
V_DD = 15V
V_DD = 5V
V_DD = 10V
V_DD = 15V
V_DD = 5V
V_DD = 10V
V_DD = 15V
V_DD = 5V
V_DD = 10V
V_DD = 15V
V_DD = 5V
V_DD = 10V
V_DD = 15V
V_DD = 5V
V_DD = 10V
V_DD = 15V
V_DD = 5V
V_DD = 10V
V_DD = 15V
Per Package
(Note 5)
200
400
ns
75
150
ns
50
100
ns
200
400
ns
80
160
ns
60
120
ns
175
350
ns
80
160
ns
65
130
ns
225
450
ns
100
200
ns
75
150
ns
100
200
ns
50
100
ns
40
80
ns
100
200
ns
50
100
ns
40
80
ns
200
400
ns
100
200
ns
65
125
ns
75
150
ns
40
75
ns
25
50
ns
40
80
ns
20
40
ns
15
30
ns
60
120
ns
30
60
ns
25
50
ns
−15
50
ns
0
30
ns
0
20
ns
−50
15
ns
−20
10
ns
−15
5
ns
100
pF
C_IN
Input Capacitance
Any Input
Note 4: AC Parameters are guaranteed by DC correlated testing.
5.0
7.5
pF
Note 5: Dynamic power dissipation (P_D) is given by: P_D = (C_PD + C_L) V_CC2f + P_Q; where C_L = load capacitance; f = frequency of operation; for further details,
see Application Note AN-90, “Family Characteristics”.
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