CD4021BC_02 Datasheet, PDF (4/7 Pages) Fairchild Semiconductor – 8-Stage Static Shift Register

AC Electrical Characteristics (Note 6)
T_A = 25°C, input t_r, t_f = 20 ns, C_L = 50 pF, R_L = 200 kΩ
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t_PLH, t_PHL
t_THL, t_TLH
f_CL
t_W
t_rCL, t_fCL
t_s
t_H
t_WH
t_REM
C_I
C_PD
Propagation Delay Time
Transition Time
Maximum Clock
Input Frequency
Minimum Clock
Pulse Width
Clock Rise and
Fall Time (Note 6)
Minimum Set-Up Time
V_DD = 5V
V_DD = 10V
V_DD = 15V
V_DD = 5V
V_DD = 10V
V_DD = 15V
V_DD = 5V
V_DD = 10V
V_DD = 15V
V_DD = 5V
V_DD = 10V
V_DD = 15V
V_DD = 5V
V_DD = 10V
V_DD = 15V
Serial Input
t_H ≥ 200 ns
(Ref. to CL)
Parallel Inputs
t_H ≥ 200 ns
(Ref. to P/S)
Minimum Hold Time
Serial In, Parallel In, t_s ≥ 400 ns
Parallel/Serial Control
Minimum P/S
Pulse Width
Minimum P/S Removal
Time (Ref. to CL)
Average Input Capacitance
V_DD = 5V
V_DD = 10V
V_DD = 15V
V_DD = 5V
V_DD = 10V
V_DD = 15V
V_DD = 5V
V_DD = 10V
V_DD = 15V
V_DD = 5V
V_DD = 10V
V_DD = 15V
V_DD = 5V
V_DD = 10V
V_DD = 15V
Any Input
Power Dissipation
Capacitance (Note 8)
240
350
100
175
70
140
100
200
50
100
40
80
2.5
3.5
5
10
8
16
100
200
50
100
40
80
15
15
15
60
120
40
80
30
60
25
50
15
30
10
20
0
10
15
150
250
75
125
50
100
100
200
50
100
40
80
5
7.5
100
ns
ns
MHz
ns
µs
ns
ns
ns
ns
ns
pF
pF
Note 6: AC Parameters are guaranteed by DC correlated testing.
Note 7: If more than one unit is cascaded t_rCL should be made less than or equal to the fixed propagation delay of the output of the driving stage for the esti-
mated capacitive load.
Note 8: C_PD determines the no load AC power consumption of any CMOS device. For complete explanation, see 74C family characteristics application note
AN-90.
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