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CD4017BC Datasheet, PDF (4/7 Pages) Fairchild Semiconductor – Decade Counter/Divider with 10 Decoded Outputs . Divide-by-8 Counter/Divider with 8 Decoded Outputs
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AC Electrical Characteristics (Note 4)
TA= 25°C, CL= 50 pF, RL= 200k, trCL and tfCL= 20 ns, unless otherwise specified
Symbol
Parameter
Conditions
Min
CLOCK OPERATION
tPHL, tPLH Propagation Delay Time Carry Out Line
Carry Out Line
Decode Out Lines
tTLH, tTHL Transition Time Carry Out and Decode Out Lines
tTLH
tTHL
fCL
Maximum Clock Frequency
tWL, tWH Minimum Clock Pulse Width
trCL, tfCL Clock Rise and Fall Time
tSU
Minimum Clock Inhibit Data Setup Time
CIN
Average Input Capacitance
Note 4: AC Parameters are guaranteed by DC correlated testing.
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
CL = 15 pF
Measured with
1.0
Respect to Carry 2.5
Output Line
3.0
Typ
Max
Units
415
800
ns
160
320
ns
130
250
ns
240
480
ns
85
170
ns
70
140
ns
500
1000
ns
200
400
ns
160
320
ns
200
360
ns
100
180
ns
80
130
ns
100
200
ns
50
100
ns
40
80
ns
2
MHz
5
MHz
6
MHz
125
250
ns
45
90
ns
35
70
ns
20
µs
15
µs
5
µs
120
240
ns
40
80
ns
32
65
ns
5
7.5
pF
AC Electrical Characteristics (Note 4)
TA = 25°C, CL = 50 pF, RL = 200k, trCL and tfCL = 20 ns, unless otherwise specified
Symbol
Parameter
Conditions
RESET OPERATION
tPHL, tPLH
Propagation Delay Time
Carry Out Line
Carry Out Line
Decode Out Lines
tW
tREM
Minimum Reset
Pulse Width
Minimum Reset
Removal Time
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
CL = 15 pF
Min
Typ
Max
Units
415
800
ns
160
320
ns
130
250
ns
240
480
ns
85
170
ns
70
140
ns
500
1000
ns
200
400
ns
160
320
ns
200
400
ns
70
140
ns
55
110
ns
75
150
ns
30
60
ns
25
50
ns
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