CD4014BC Datasheet, PDF (4/7 Pages) Fairchild Semiconductor – 8-Stage Static Shift Register

AC Electrical Characteristics (Note 5)
T_A = 25°C, input t_r, t_f = 20 ns, C_L = 50 pF, R_L = 200 kΩ
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t_PHL, t_PLH
t_THL, t_TLH
f_CL
t_W
t_rCL, t_fCL
t_S
t_H
C_I
Propagation Delay Time
Transition Time
Maximum Clock
Input Frequency
Minimum Clock
Pulse Width
Clock Rise and
Fall Time (Note 6)
Minimum Set-Up Time
(Note 7) Serial Input
t_H ≥ 200 ns
Parallel Inputs
t_H ≥ 200 ns
Parallel/Serial Control
t_H ≥ 200 ns
Minimum Hold Time
Serial In, Parallel In, t_S ≥ 400 ns
Parallel/Serial Control
Average Input Capacitance
V_DD = 5V
V_DD = 10V
V_DD = 15V
V_DD = 5V
V_DD = 10V
V_DD = 15V
V_DD = 5V
V_DD = 10V
V_DD = 15V
V_DD = 5V
V_DD = 10V
V_DD = 15V
V_DD = 5V
V_DD = 10V
V_DD = 15V
V_DD = 5V
V_DD = 10V
V_DD = 15V
V_DD = 5V
V_DD = 10V
V_DD = 15V
V_DD = 5V
V_DD = 10V
V_DD = 15V
V_DD = 5V
V_DD = 10V
V_DD = 15V
Any Input
(Note 8)
200
320
ns
80
160
ns
60
120
ns
100
200
ns
50
100
ns
40
80
ns
2.8
4
MHz
6
12
MHz
8
16
MHz
90
180
ns
40
80
ns
25
50
ns
15
µs
15
µs
15
µs
60
120
ns
40
80
ns
30
60
ns
80
160
ns
40
80
ns
30
60
ns
100
200
ns
50
100
ns
40
80
ns
0
ns
10
ns
15
ns
5
7.5
pF
C_PD
Power Dissipation Capacitance
(Note 8)
110
pF
Note 5: AC Parameters are guaranteed by DC correlated testing.
Note 6: If more than one unit is cascaded t_rCL should be made less than or equal to the fixed propagation delay of the output of the driving stage for the esti-
mated capacitive load.
Note 7: Setup times are measured with reference to clock and a fixed hold time (t_H) as specified.
Note 8: C_PD determines the no load AC power consumption of any CMOS device. For complete explanation, see 74C family characteristics application note
AN-90.
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