AN-3012 Datasheet, PDF (4/8 Pages) Fairchild Semiconductor – High Speed Logic Compatible

AN-3012
APPLICATION NOTE
Figure 9 provides insight on how the pulse width distortion
changes with temperature. The typical pulse width
distortion, PWD, [t_PHL – t_PLH] is 2ns. These performance
characteristics allow high serial data (> 20Mbaud)
communication through the optocoupler.
10
Frequency = 5MHz
Duty Cycle = 50%
5
IF = 10mA
RL= 350Ω
0
VCC = 5.0V
-5
-10
VCC = 3.3V
-15
-20
-25
-40 -20
0
20
40 60
80 100 120
TA – AMBIENT TEMPERATURE (°C)
Figure 9. Pulse Width Distortion vs Temperature
There are various assumptions which are made in relation
of switching speed to baud rate, such as binary
Non-Return-Zero (NRZ) data stream, 1 bit time equating
1 baud (or signaling rate) and a square wave pattern.
Therefore, a 5MHz square wave (duty factor of 50%) is a
10Mbit or 10MBaud signal.
For serial communications (RS standards), propagation
delay only affects latency or data throughput. The maximum
data rate is related to PWD performance and the number of
samples per bit used by the UART to validate the 1 or 0 data.
The minimum acceptable sample rate is 4, which is half the
Nyquist recommended rate. Thus, the recommended
maximum data rate is usually 4 times that of the PWD. In the
case of FODM8061, with a maximum PWD of 25ns the
maximum data rate is 10MBd.
Ideally, the delay skew, t_PSK, should be specified at about
2 times the maximum PWD. It is important to note that
t_PSK is equal to the magnitude of the worst case difference
in t_PHL and/or t_PLH that will be seen between any two units
from the same manufacturing date code that are operated
at same operating conditions; same case temperature, equal
loads (R_L = 350Ω and C_L = 15pF), and with an input rise
time less than 5ns.
Signal Performance
One of the best indicators of data communication signal
quality is an eye diagram. The eye diagram is created by
driving the LED with a pseudorandom binary data sequence,
PRBS, and triggering the scope with the serial data clock.
Figure 10 shows a 10MBd eye diagram using the test circuit
found in Figure 7. This diagram shows a duty cycle
distortion of only 2.18ns. This is very close to the typical
PWD of 2ns. The LED current was adjusted for optimal
crossing, under this condition, the rise and fall times are
symmetrical and less than 20ns.
Figure 10. 10MBd Eye Diagram
Figure 11 illustrates the typical and respectable eye diagram
for 20MBd PRBS data.
Figure 11. 20MBd Eye Diagram
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REV. 1.0 3/9/10