SPT7750 Datasheet, PDF (3/8 Pages) Fairchild Semiconductor – 8-BIT, 500 MSPS, FLASH A/D CONVERTER

ELECTRICAL SPECIFICATIONS
T_J = T_C = T_A = +25 °C , V_EE=–5.2 V, V_RB=–2.0 V, V_RM=–1.0 V, V_RT=0.00 V, ƒ_CLK=500 MHz, Duty Cycle=50%, unless otherwise specified.
PARAMETERS
TEST
CONDITIONS
TEST
SPT7750A
SPT7750B
LEVEL MIN TYP MAX MIN TYP MAX UNITS
Dynamic Performance
Spurious Free Dynamic Range
ƒ_IN = 50 MHz
ƒ_IN = 250 MHz
I
49
I
41
44
dB
36
dB
Digital Inputs
Input High Voltage
(CLK, CLK)
Input Low Voltage
(CLK, CLK)
Clock Pulse Width High (t_PWH)
Clock Pulse Width Low (t_PWL)
I
–1.1 –0.7
–1.1 –0.7
V
I
–1.8 –1.5
–1.8 –1.5 V
I
1.0 0.67
1.0 0.67
ns
I
1.0 0.67
1.0 0.67
ns
Digital Outputs
Logic 1 Voltage
Logic 0 Voltage
Rise Time
Fall Time
20% to 80%
20% to 80%
I
–1.1 –0.9
–1.1 –0.9
V
I
–1.8 –1.5
–1.8 –1.5 V
V
450
450
ps
V
450
450
ps
Power Supply Requirements
Voltage V_EE
Current I_EE
Power Dissipation
IV –4.95 –5.2 –5.45 –4.95 –5.2 –5.45 V
I
1.05 1.2
1.05 1.2 A
I
5.5 6.25
5.5 6.25 W
Typical Thermal Impedance: θ_JC = +4 °C/W.
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions:
All parameters having min/max specifications
are guaranteed. The Test Level column indi-
cates the specific device testing actually per-
formed during production and Quality Assur-
ance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
Unless otherwise noted, all test are pulsed
tests; therefore, T_J = T_C = T_A.
LEVEL
I
II
III
IV
V
VI
TEST PROCEDURE
100% production tested at the specified temperature.
100% production tested at T_A = +25 °C, and sample tested at the
specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design and characteri-
zation data.
Parameter is a typical value for information purposes only.
100% production tested at T_A = +25 °C. Parameter is guaranteed
over specified temperature range.
SPT7750
3
11/30/01