FIN1101 Datasheet, PDF (3/6 Pages) Fairchild Semiconductor – LVDS Single Port High Speed Repeater

AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol
Parameter
Test Conditions
Min
Typ
Max
(Note 3)
Units
t_PLHD
Differential Propagation Delay
LOW-to-HIGH
0.75
1.1
1.75
ns
t_PHLD
Differential Propagation Delay
HIGH-to-LOW
R_L = 100 Ω, C_L = 5 pF,
V_ID = 200 mV to 450 mV,
0.75
1.1
1.75
ns
t_TLHD
Differential Output Rise Time (20% to 80%)
V_IC = |V_ID|/2 to (V_CC− (V_ID/2),
0.29
0.40
0.58
ns
t_THLD
Differential Output Fall Time (80% to 20%)
Duty Cycle = 50%,
0.29
0.40
0.58
ns
t_SK(P)
Pulse Skew |t_PLH - t_PHL|
See Figure 3 and Figure 4
0.01
0.2
ns
t_SK(PP)
Part-to-Part Skew (Note 4)
0.5
ns
f_MAX
Maximum Frequency (Note 5)(Note 6)
400
800
MHz
t_PZHD
Differential Output Enable Time from Z to HIGH
2.1
5
ns
t_PZLD
Differential Output Enable Time from Z to LOW R_L = 100 Ω, C_L = 5 pF,
2.3
5
ns
t_PHZD
Differential Output Disable Time from HIGH to Z See Figure 2 and Figure 3
1.5
5
ns
t_PLZD
t_DJ
Differential Output Disable Time from LOW to Z
LVDS Data Jitter,
V_ID = 300 mV, PRBS = 2²³ − 1,
Deterministic
V_IC = 1.2V at 800 Mbps
1.8
5
ns
85
135
ps
t_RJ
LVDS Clock Jitter, Random
(RMS)
V_ID = 300 mV
V_IC = 1.2 V at 400 MHz
2.1
3.5
ps
Note 3: All typical values are at T_A = 25°C and with V_CC = 3.3V, V_ID = 300mV, V_IC = 1.2V unless otherwise specified.
Note 4: t_SK(PP) is the magnitude of the difference in differential propagation delay times between identical channels of two devices switching in the same
direction (either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test cir-
cuits.
Note 5: Passing criteria for maximum frequency is the output V_OD > 200 mV and the duty cycle is 45% to 55% with all channels switching.
Note 6: Output loading is transmission line environment only; C_L is < 1 pF of stray test fixture capacitance.
FIGURE 1. Differential Receiver Voltage Definitions and
Propagation I and Transition Time Test Circuit
FIGURE 2. Differential Driver DC Test Circuit
Note A: All LVDS input pulses have frequency = 10MHz, t_R or t_F < = 0.5 ns
Note B: C_L includes all probe and test fixture capacitances
FIGURE 3. Differential Driver Propagation Delay and Transition Time Test Circuit
3
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