FDMF6824A Datasheet, PDF (3/19 Pages) Fairchild Semiconductor – FDMF6824A — Extra-Small, High-Performance, High-Frequency DrMOS Module

Pin Configuration
PWM
DISB#
THWN#
CGND
GL
VSWH
VSWH
VSWH
VSWH
VSWH
1 2 3 4 5 6 7 8 9 10
CGND
VIN
41
42
VSWH
43
30 29 28 27 26 25 24 23 22 21
VIN
VIN
VIN
VIN
VSWH
PGND
PGND
PGND
PGND
PGND
VIN
VIN
VIN
VIN
VSWH
PGND
PGND
PGND
PGND
PGND
10 9 8 7 6 5 4 3 2 1
VIN
CGND
42
41
VSWH
43
21 22 23 24 25 26 27 28 29 30
PWM
DISB#
THWN#
CGND
GL
VSWH
VSWH
VSWH
VSWH
VSWH
Figure 3. Bottom View
Figure 4. Top View
Pin Definitions
Pin # Name
Description
When SMOD#=HIGH, the low-side driver is the inverse of the PWM input. When
1
SMOD# SMOD#=LOW, the low-side driver is disabled. This pin has a 10 µA internal pull-up current
source. Do not add a noise filter capacitor.
2
VCIN IC bias supply. Minimum 1 µF ceramic capacitor is recommended from this pin to CGND.
3
VDRV
Power for the gate driver. Minimum 1 µF ceramic capacitor is recommended to be connected
as close as possible from this pin to CGND.
4
BOOT
Bootstrap supply input. Provides voltage supply to the high-side MOSFET driver. Connect a
bootstrap capacitor from this pin to PHASE.
5, 37, 41 CGND IC ground. Ground return for driver IC.
6
GH For manufacturing test only. This pin must float; it must not be connected to any pin.
7
PHASE Switch node pin for bootstrap capacitor routing. Electrically shorted to VSWH pin.
8
NC
No connect. The pin is not electrically connected internally, but can be connected to VIN for
convenience.
9 - 14, 42 VIN Power input. Output stage supply voltage.
15, 29 -
35, 43
VSWH
Switch node input. Provides return for high-side bootstrapped driver and acts as a sense point
for the adaptive shoot-through protection.
16 – 28 PGND Power ground. Output stage ground. Source pin of the low-side MOSFET.
36
GL For manufacturing test only. This pin must float; it must not be connected to any pin.
38
THWN#
Thermal warning flag, open collector output. When temperature exceeds the trip limit, the
output is pulled LOW. THWN# does not disable the module.
Output disable. When LOW, this pin disables the power MOSFET switching (GH and GL are
39
DISB# held LOW). This pin has a 10 µA internal pull-down current source. Do not add a noise filter
capacitor.
40
PWM PWM signal input. This pin accepts a three-state 5 V PWM signal from the controller.
© 2013 Fairchild Semiconductor Corporation
FDMF6824A • Rev. 1.0.1
3
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