FAN6861 Datasheet, PDF (3/15 Pages) Fairchild Semiconductor – Low-Cost, Highly Integrated, Green-Mode PWM Controller for Peak Power Management

Marking Information
Pin Configuration
AAR: FAN6861
TT: Wafer lot code
• • •: Year code
_ _ _: Week code
Figure 3. Top Mark
Figure 4. Pin Configuration
Pin Definitions
Pin #
1
2
3
4
5
6
Name Description
GND Ground.
This pin is internally connected to the inverting input of the PWM comparator. The collector of
FB
an opto-coupler is typically tied to this pin. For stable operation, a capacitor should be placed
between this pin and GND. If the voltage of this pin is higher than 4.6V for longer than 780ms,
the overload protection is triggered and PWM output is disabled.
This pin is for programmable over-temperature protection. An external NTC thermistor is
RT connected between this pin and GND pin. Once the voltage of this pin drops below a threshold
of 0.7V, PWM output is disabled.
SENSE
This pin is for current sense. This pin senses the voltage across a resistor. The voltage of this
pin is compared with the feedback information determining the PWM duty cycle.
VDD This pin is the positive supply voltage input.
GATE
The totem-pole output driver to drive the gate of power MOSFET. Soft driving waveform is
implemented to reduce EMI.
© 2009 Fairchild Semiconductor Corporation
FAN6861 • Rev. 1.0.1
3
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