FAN6206 Datasheet, PDF (3/15 Pages) Fairchild Semiconductor – Highly Integrated Dual-Channel Synchronous Rectification Controller

Marking Information
Pin Configuration
F: Fairchild Logo
Z: Plant Code
X: Year Code
Y: Week Code
TT: Package Type
T: M=SOP
P: Y: Green Package
M: Manufacture Flow Code
Figure 3. Top Mark
Figure 4. Pin Configuration
Pin Definitions
Pin #
1,2
3
4
5
6
7
8
Name
LPC1,
LPC2
SN
SP
VDD
GATE2
GND
GATE1
Description
Winding detection. This pin is used to detect the voltage on the winding during the on-time
period of the primary GATE. An internal current source, ICHG, is determined according to the
voltage on the DET pin.
Synchronized signal to turn on SR. This pin is used to receive the “XN” signal from the primary
side to turn off the SR gate.
Synchronized signal to turn on SR. This pin is used to receive the “XP” signal from the primary-
side to turn-on the SR gate.
Power supply pin. The threshold voltages for startup and turn-off are 8.5V and 7.5V,
respectively.
Driver output for freewheeling synchronous rectifier MOSFET.
Ground
Driver output for rectifying synchronous rectifier MOSFET.
© 2010 Fairchild Semiconductor Corporation
FAN6206 • Rev. 1.0.2
3
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