DM7476_01 Datasheet, PDF (3/4 Pages) Fairchild Semiconductor – Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs

Switching Characteristics
at V_CC = 5V and T_A = 25°C
Symbol
Parameter
f_MAX
t_PHL
t_PLH
t_PHL
t_PLH
t_PHL
t_PLH
Maximum Clock Frequency
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
From (Input)
To (Output)
Preset to Q
Preset to Q
Clear to Q
Clear to Q
Clock to Q or Q
Clock to Q or Q
R_L = 400Ω, C_L = 15 pF
Min
Max
15
40
25
40
25
40
25
Units
MHz
ns
ns
ns
ns
ns
ns
3
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