CD4016BC_02 Datasheet, PDF (3/9 Pages) Fairchild Semiconductor – Quad Bilateral Switch

AC Electrical Characteristics (Note 4)
T_A = 25°C, t_r = t_f = 20 ns and V_SS = 0V unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t_PHL, t_PLH
Propagation Delay Time
Signal Input to Signal Output
t_PZH, t_PZL
t_PHZ, t_PLZ
Propagation Delay Time
Control Input to Signal
Output HIGH Impedance to
Logical Level
Propagation Delay Time
Control Input to Signal
Output Logical Level to
HIGH Impedance
Sine Wave Distortion
V_C = V_DD, C_L = 50 pF, (Figure 1)
R_L = 200k
V_DD = 5V
V_DD= 10V
V_DD = 15V
R_L = 1.0 kΩ, C_L = 50 pF, (Figure 2, Figure 3)
V_DD = 5V
V_DD = 10V
V_DD = 15V
R_L = 1.0 kΩ, C_L = 50 pF, (Figure 2, Figure 3)
V_DD = 5V
V_DD = 10V
V_DD = 15V
V_C = V_DD = 5V, V_SS = −5
R_L = 10 kΩ, V_IS = 5 V_P-P, f = 1 kHz,
(Figure 4)
58
100
ns
27
50
ns
20
40
ns
20
50
ns
18
40
ns
17
35
ns
15
40
ns
11
25
ns
10
22
ns
0.4
%
Frequency Response — Switch
“ON” (Frequency at −3 dB)
V_C = V_DD = 5V, V_SS = −5V,
R_L = 1 kΩ, V_IS = 5 V_P-P,
20 Log₁₀ V_OS/V_OS (1 kHz) −dB,
(Figure 4)
40
MHz
Feedthrough — Switch “OFF”
(Frequency at −50 dB)
V_DD = 5V, V_C = V_SS = −5V,
R_L = 1 kΩ, V_IS = 5 V_P-P,
20 Log₁₀ (V_OS/V_IS) = −50 dB,
(Figure 4)
1.25
MHz
Crosstalk Between Any Two
Switches (Frequency at −50 dB)
V_DD = V_C(A) = 5V; V_SS = V_C(B) = −5V,
R_L = 1 kΩV_IS(A) = 5 V_P-P,
20 Log₁₀ (V_OS(B)/V_OS(A) ) = −50 dB,
(Figure 5)
0.9
MHz
Crosstalk; Control Input to
V_DD = 10V, R_L = 10 kΩ
Signal Output
R_IN = 1 kΩ, V_CC = 10V Square Wave,
C_L = 50 pF (Figure 6)
Maximum Control Input
R_L = 1 kΩ, C_L = 50 pF, (Figure 7)
V_OS(f) = ½ V_OS(1 kHz)
V_DD = 5V
V_DD = 10V
V_DD = 15V
C_IS
Signal Input Capacitance
C_OS
Signal Output Capacitance
V_DD = 10V
C_IOS
Feedthrough Capacitance
V_C = 0V
C_IN
Control Input Capacitance
Note 4: AC Parameters are guaranteed by DC correlated testing.
150
mV_P-P
6.5
8.0
9.0
4
4
0.2
5
7.5
MHz
MHz
MHz
pF
pF
pF
pF
Note 5: These devices should not be connected to circuits with the power “ON”.
Note 6: In all cases, there is approximately 5 pF of probe and jig capacitance on the output; however, this capacitance is included in C_L wherever it is
specified.
Note 7: V_IS is the voltage at the in/out pin and V_OS is the voltage at the out/in pin. V_C is the voltage at the control input.
3
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