CCD595_04 Datasheet, PDF (3/7 Pages) Fairchild Semiconductor – 9216 x 9216 Pixel Image Area 9216 x 9216 Pixel Image Area

PRELIMINARY DATA SHEET
Array Size
Pixel Size
Image Format
Number of Outputs
Pixel Output Rate
Number of Phases
Number of Prescan Pixels
Number of Overscan Lines
Total Number of Lines
Number of Phases
Pixel Rate per Output
DEVICE ARCHITECTURE
9216 x 9216
Full Frame
8.75-um x 8.75-um
80.64 x 80.64
Mm
8 (4 Upper, 4 Lower)
Current Configuration Wired for 4 outputs
100MHz (25MHz per output)
3 + 3 (TG clocks)
3
Pixels/line
19
Top and Bottom
9216
2
Horizontal
25MHz
Typical
SYMBOL
V_DD
V_RD
V_OG
V_SS
V_odc
Z
DC OPERATING CHARACTERISTICS
PARAMETER
RANGE
MIN NOM
MAX
DC Supply Voltage
18.0
20.0
23.0
Reset Drain Voltage
14.0
17.0
20.0
Output Gate Voltage
4.0
Substrate Ground
0.0
Output DC Level
VRD-5
VRD-4
Suggested Load Resistor
0.8
1.0
1.8
UNIT
V
V
V
V
K ohms
REMARKS
SYMBOL PARAMETER
TYPICAL CLOCK VOLTAGES
HIGH LOW UNIT REMARKS
Vφ_H(1,2),
φSG
VφV _(1,2,3)
VφR
Vφ_{VTG (2,3)}
CφV_(1,2,3)
CφVTG_2,3
Horizontal Transport Clock Voh Max-Min
Horizontal Transport Clock Voh Max-Min
Vertical Transport Clocks
Reset Gate Clock
Array Transfer Gate Clock
Vertical Array Gates
A₁
Cap. (per φV)
A₂
A₃
Array Transfer Gate
TG₂
Cap. (per pin)
TG₃
+7.5
+6
+8.0
+6.0
+8.0
47
86
109
200
200
-7.5 V
-2
V
-12.0 V
+1.0 V
-12.0 V
30
nF
38
31
150
pF
150
+4.5, -0.5 Typical
+5, -11 V Typical
+2.0 +8.0 V Typical
+5, -11 Typical
Min @ +10V
Max @ -10V
Min @ +10V
Max @ -10V
CφH _(1,2)
Horizontal Transfer Gate
S₁ 65
PF
Cap. (per φ H)
S₂ 76
Note 1: φH = 400 pF, φV = 60,000 pF. All φH clock rise and fall times should be > 10 ns.
Min @ +10V (per output)
Max @ -10V (per output)
PERFORMANCE SPECIFICATIONS
SYMBOL PARAMETER
RANGE
UNIT
MIN NOM MAX
REMARKS
V_sat
Q_sat
S_V
H_sat
PRNU
DSNU
DC
Saturation Output Voltage
Full Well Capacity (98% of Pixels)
Output Amp Sensitivity
Horizontal Register Capacity
Photo Response Non-Uniformity, Peak-to-Peak
Dark Signal Non-Uniformity (RMS)
Average Dark Current
350
600
750
70,000
5
9
11
100,000
+10
5.0
0.5
mV
e-
µV/e-
e-
%V_SAT
mV
nA/cm²
Note 1
Note 1
Note 2
Note 3
Note 3
QE_A
MTF
Average Quantum Efficiency (550 – 800µm)
MTF at Nyquist
0.35
0.50
%
%
Note 4
V_cte
Vertical Transfer Efficiency
0.999995
Per Transfer (each phase) Note 2
H_cte
Horizontal Charge Transfer Efficiency
0.99995
Per Transfer (each phase) Note 2
NE
Total Read Noise Electrons
20
30 e-rms Less Shot Noise Note 6
fMAX_H
PD
H Clock Frequency
Power Dissipation On Chip
25
MHz
2.9
W
At 25MHz each register
Note 1: Minimum output voltage and/or well capacity is achieved operating in standard test condition mode and is the level above which saturation
non-linearity of 50% from best straight line fit occurs.
Note 2: Measured at approximately 50% V_sat.
Note 3: Value shown is for 15°C.
Note 4: Measured at the format center with 2854K tungsten source and Schott OG550 filter, 3mm thick.
Note 5: Standard test conditions are non-MPP clocks and DC operating voltages with 25MHz serial output rate/port.
Note 6: Measured in dark with correlated double sampling of amplifier output signal.
1801 McCarthy Blvd, Milpitas 95035 • 800-325-6975 • Fax [phone] • www.fairchildimaging.com • Rev A1 • 3 of 7